Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating

1. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and having the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and

wherein said floating body is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

2. The semiconductor memory cell of claim 1 , wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

3. The semiconductor memory cell of claim 1 , wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

4. The semiconductor memory cell of claim 1 , further comprising a control gate positioned above said trapping layer.

5. The semiconductor memory cell of claim 1 , wherein the semiconductor memory cell functions as a binary cell.

6. The semiconductor memory cell of claim 1 , wherein the semiconductor memory cell functions as a multi-level cell.

7. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and

wherein charge flow into said floating body upon restoration of power to said memory cell depends on charge stored in said one of said first and second storage locations in said trapping layer so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

8. The semiconductor memory cell of claim 7 , wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

9. The semiconductor memory cell of claim 7 , wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

10. The semiconductor memory cell of claim 7 , further comprising a control gate positioned above said trapping layer.

11. The semiconductor memory cell of claim 7 , wherein the semiconductor memory cell functions as a binary cell.

12. The semiconductor memory cell of claim 7 , wherein the semiconductor memory cell functions as a multi-level cell.

13. A memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said cells each comprising:

a floating body region to store charge as volatile memory;

first and second regions;

a trapping layer positioned in between the first and second locations and above a surface of the floating body region; the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another;

wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

14. The semiconductor memory array of claim 13 , wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

15. The semiconductor memory array of claim 13 , wherein said floating body is configured to a predetermined state prior to being charged based on charge stored in said one of said first and second storage locations in said trapping layer.

16. The semiconductor memory array of claim 13 , wherein said cells further comprise control gates positioned above said trapping layers, respectively.

17. The semiconductor memory array of claim 13 , wherein the semiconductor memory array functions as a binary cell memory array.

18. The semiconductor memory array of claim 13 , wherein the semiconductor memory array functions as a multi-level cell memory array.