IP Library Granted Patent US 7,674,669
Granted Patent B2
US 7,674,669 · App. 11/851,993 · Granted Mar 9, 2010

FIN field effect transistor

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,674,669
App. No.
11/851,993
Granted
Mar 9, 2010
Kind
B2
Abstract

Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si 1-X Ge X ) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.

Claims (25)

1. A method for forming a FinFET, comprising:

forming a relaxed silicon germanium (Si 1-X Ge X ) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;

forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation; and

forming a gate opposing the body region and separated therefrom by a gate dielectric,

wherein the method includes epitaxially growing a germanium (Ge) layer on a sidewall on the body region to provide biaxial compressive strain to the body region in forming a PMOS FinFET.

2. The method of claim 1 , wherein the method includes epitaxially growing the Ge layer on the sidewall on the body region to a thickness of approximately 12 nm.

3. The method of claim 1 , wherein the method includes forming a channel between the source and the drain having a width less than 35 nm and a length less than 25 nanometers.

4. The method of claim 1 , wherein forming the source and the drain with halo ion implantation includes:

forming a p-type source and drain having a Boron (B) dopant at a concentration of 2×10 20 atoms/cm 3 ; and

forming a halo ion implant underneath the p-type source drain having a concentration of 2×10 18 atoms/cm 3 .

5. The method of claim 1 , wherein forming the source and the drain with halo ion implantation includes:

forming an n-type source and drain having an Arsenic (As) dopant at a concentration of 2×10 20 atoms/cm 3 ; and

forming a halo ion implant underneath the n-type source and drain having a concentration of 2×10 18 atoms/cm 3 .

6. A method for forming a FinFET, comprising:

forming a relaxed silicon germanium (Si 1-X Ge X ) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;

forming a substitute gate over the body region;

forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation;

annealing the source and the drain before removing the substitute gate; and

forming a gate separated from the body region by a gate dielectric.

7. The method of claim 6 , wherein the method includes forming a source extension and a drain extension while the substitute gate is present on the device.

8. The method of claim 6 , wherein the method includes epitaxially growing a germanium (Ge) sidewall on the body region to provide biaxial compressive strain on the body region in forming a PMOS FinFET.

9. The method of claim 6 , wherein the method includes epitaxially growing a silicon (Si) sidewall on the body region to provide biaxial tensile strain on the body region in forming an NMOS FinFET.

10. The method of claim 6 , wherein forming the relaxed silicon germanium (Si 1-X Ge X ) body region includes forming a forming a relaxed silicon germanium (Si 1-X Ge X ) where X is in a range of 0.5 to 0.6.

11. The method of claim 6 , wherein annealing the source and the drain before removing the substitute gate includes annealing at a temperature in a range of 850 degrees Celsius to 1050 degrees Celsius for a period of at least 5 seconds to activate the source and the drain.

12. The method of claim 11 , wherein forming the gate includes forming a metal gate separated from the body region by a dielectric material having a dielectric constant (K) greater than 12.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2007
From: HANAFI, HUSSEIN I.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 019799/0473 →
Continuity (1)
Related Publication 20090065853A1 · Mar 12, 2009