Semiconductor device and method for fabricating the same

1. A semiconductor device comprising:

a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region;

first and second lower electrodes disposed in the first and second regions, respectively;

first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively;

an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns;

a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern; and

an upper electrode disposed on a surface of the dielectric layer,

wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

2. The semiconductor device of claim 1 , wherein a lower surface of the first lower support pattern and a lower surface of the second lower support pattern are disposed on substantially the same plane.

3. The semiconductor device of claim 1 , wherein the upper support pattern comprises a first opening, the first lower support pattern comprises a second opening, and the second opening has a shape which is transferred from the first opening.

4. The semiconductor device of claim 3 , wherein the thickness of the first lower support pattern increases as thickness measurement location of the first lower support pattern goes away from the second opening.

5. The semiconductor device of claim 1 , wherein the thickness of the second lower support pattern is about 250 Å to 300 Å.

6. The semiconductor device of claim 5 , wherein the thickness of the first lower support pattern is about 80 Å to 200 Å.

7. The semiconductor device of claim 1 , further comprising:

a third lower electrode disposed in the second region, and further spaced apart from the first region as compared with the second lower electrode; and

a third lower support pattern disposed on an outer wall of the third lower electrode,

wherein thickness of the third lower support pattern is larger than the thickness of the second lower support pattern.

8. The semiconductor device of claim 1 , wherein an upper surface of the upper support pattern and upper surfaces of the first and second lower electrodes are disposed on substantially the same plane.

9. The semiconductor device of claim 1 , further comprising:

a unit active region disposed in the substrate, and comprising first and second source/drain regions;

a word line disposed between the first and second source/drain regions; and

first and second contact plugs electrically connected to the first and second source/drain regions, respectively,

wherein the first contact plug is electrically connected to a bit line, and

the second contact plug is electrically connected to the first lower electrode.

10. The semiconductor device of claim 9 , wherein each of a plurality of first and second lower electrodes is disposed on the substrate, and the plurality of first and second lower electrodes are arranged in a form of a honeycomb.

11. The semiconductor device of claim 1 , wherein the first and second lower electrodes have cylinder shapes.

12. A semiconductor device comprising:

a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region;

a lower electrode disposed in the cell region, and extending in a first direction intersecting with the substrate;

a lower support pattern disposed on an outer wall of the lower electrode;

an upper support pattern disposed on an outer wall of the lower electrode, and being on and spaced apart from the lower support pattern in the first direction;

a dielectric layer disposed on surfaces of the lower electrode, the lower support pattern, and the upper support pattern; and

first and second upper electrodes disposed on a surface of the dielectric layer of the first and second regions, respectively,

wherein a length of the first upper electrode extending in the first direction between the lower support pattern and the upper support pattern is larger than a length of the second upper electrode extending in the first direction between the lower support pattern and the upper support pattern.

13. The semiconductor device of claim 12 , wherein upper surface of the first upper electrode extending in the first direction between the lower support pattern and the upper support pattern and upper surface of the second upper electrode extending in the first direction between the lower support pattern and the upper support pattern are disposed on substantially the same plane.

14. The semiconductor device of claim 12 , further comprising:

a third upper electrode disposed in the second region, and further spaced apart from the first region as compared with the second upper electrode,

wherein a length of the third upper electrode extending in the first direction between the lower support pattern and the upper support pattern is smaller than the length of the second upper electrode extending in the first direction between the lower support pattern and the upper support pattern.

15. The semiconductor device of claim 12 , wherein the first and second upper electrodes are disposed on the surface of the dielectric layer in a conformal fashion.