Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.
1. A method for fabricating a semiconductor device, comprising:
forming a first redistribution layer (RDL) structure on a polish stop material on a first carrier;
subjecting the first RDL structure and the first carrier to a first singulation process to separate individual interconnect components from one another;
rearranging and mounting the individual interconnect components onto a second carrier;
forming a molding compound covering the individual interconnect components;
removing the second carrier to expose a surface of the first RDL structure of each of the individual interconnect components;
forming a second RDL structure on the exposed surface of the first RDL structure and on the molding compound;
forming first connecting elements on the second RDL structure;
bonding the first connecting elements to a third carrier;
grinding the molding compound and the first carrier;
completely removing a remaining portion of the first carrier to form a recess to expose the polish stop material;
polishing the molding compound such that a top surface of the polish stop material is coplanar with a top surface of the molding compound;
forming openings in the polish stop material; and
forming second connecting elements in the openings respectively.
2. The method of claim 1 , wherein after forming the second connecting elements in the openings, respectively, the method further comprises:
mounting semiconductor dies on the second connecting elements; and
removing the third carrier; and
performing a second singulation process to thereby separate individual semiconductor packages from one another.
3. The method of claim 1 , wherein forming the first RDL structure on the polish stop material comprises forming the first RDL structure on a polish stop material comprising silicon nitride, silicon oxide, or a combination thereof.
4. The method of claim 1 , wherein forming the RDL structure on the polish stop material on the first carrier comprises forming the RDL structure on the polish stop material on a silicon carrier.
5. The method of claim 1 , wherein rearranging and mounting the individual interconnect components onto the second carrier comprises rearranging and mounting the individual interconnect components on a carrier comprising glass or silicon and having a wafer shape or a rectangular panel shape.
6. The method of claim 5 , wherein bonding the first connecting elements to the third carrier comprises bonding the first connecting elements to a carrier comprising glass or silicon and having the same shape as that of the second carrier.
7. The method of claim 2 , wherein forming the first connecting elements on the second RDL structure comprises forming BGA balls on the second RDL structure.
8. The method of claim 7 , wherein forming the first connecting element on the second RDL structure comprises forming the first connecting elements on the second RDL structure at a ball pitch that matches a ball pad pitch on a motherboard or a printed circuit board (PCB).
9. The method of claim 8 , wherein forming second connecting elements in the openings comprises forming micro bumps in the openings.
10. The method of claim 9 , wherein forming the second connecting elements in the openings comprises forming the second connecting elements at a fine pitch that matches an I/O pad pitch on an active surface of each of the semiconductor dies.
11. The method of claim 1 , wherein completely removing the remaining portion of the first carrier comprises completely removing the remaining portion of the first carrier using a wet etching or a dry etching process.
12. A method for fabricating a semiconductor device, the method comprising:
forming a first redistribution layer (RDL) structure on a polish stop layer on a first carrier;
singulating the first RDL structure and the first carrier to form two or more interconnect components each comprising the first RDL structure and the first carrier;
mounting the interconnect components on a second carrier;
forming a molding compound on the second carrier and about the interconnect components mounted on the second carrier;
removing the second carrier to expose a surface of each of the first RDL structures of the interconnect components;
forming a second RDL structure on the exposed surface of the first RDL structure;
forming first connecting elements on a side of the second RDL structure opposite which the second RDL structure is formed on the first RDL structure;
providing a third carrier over the first connecting elements;
removing the first carrier and at least a portion of the molding compound to expose the polish stop layer;
forming openings in the polish stop layer; and
forming second connecting elements in the openings in the polish stop layer.
13. The method of claim 12 , wherein forming the first connecting elements on the side of the second RDL structure opposite which the second RDL structure is formed comprises forming BGA balls on the side of the second RDL structure opposite which the second RDL structure is formed.
14. The method of claim 13 , wherein forming the first connecting elements on the second RDL structure comprises forming the first connecting elements to have a ball pitch that corresponds to a ball pad pitch of a motherboard or a printed circuit board.
15. The method of claim 12 , further comprising forming the second connecting elements to comprise micro bumps.
16. The method of claim 15 , wherein forming the second connecting elements in the openings in the polish stop layer comprises forming the second connecting elements to have a fine pitch that matches an I/O pad pitch on an active surface of a semiconductor die to be mounted on the interconnect components.
17. The method of claim 12 , further comprising mounting a first semiconductor die and a second semiconductor die on respective second connecting elements of the second connecting elements of each respective interconnect component.
18. The method of claim 17 , further comprising:
removing the third carrier; and
singulating a semiconductor structure comprising the first RDL structure on the polish stop layer, the second RDL structure, the first connecting elements, the second connecting elements, the first semiconductor die, and the second semiconductor die.
19. The method of claim 17 , wherein mounting the first semiconductor die and the second semiconductor die on respective second connecting elements comprises electrically connecting the first semiconductor die and the second semiconductor die to the first RDL structure through the second connecting elements.
20. The method of claim 12 , wherein forming the second RDL structure on the exposed surface of the first RDL structure comprises electrically connecting a rewiring layer of the first RDL structure and a rewiring layer of the second RDL structure.