Set and reset pulse generator circuit

1. A set and reset pulse generator circuit, comprising:

a set circuit that is configured to receive an input signal, to generate a voltage on a node of the set circuit using the input signal, and to generate a set pulse in accordance with the input signal, the voltage on the node of the set circuit, and a voltage on a node of a reset circuit;

the reset circuit that is configured to receive the input signal, to generate the voltage on the node of the reset circuit using the input signal, and to generate a reset pulse in accordance with the input signal, the voltage on the node of the set circuit, and the voltage on the node of the reset circuit;

a first cross-coupling circuit that is configured to couple the voltage on the node of the set circuit to the reset circuit; and

a second cross-coupling circuit that is configured to couple the voltage on the node of the reset circuit to the set circuit.

2. The set and reset pulse generator circuit of claim 1 , wherein the set circuit is configured to charge a first capacitor using the input signal to generate the voltage on the node of the set circuit, and to generate the set pulse by performing a logical operation on the input signal, the voltage on the first capacitor, and the voltage on the node of the reset circuit.

3. The set and reset pulse generator circuit of claim 2 , wherein the reset circuit is configured to invert the input signal to generate an inverted input signal, to charge a second capacitor using the inverted input signal to generate the voltage on the node of the reset circuit, and to generate the reset pulse by forming a logical operation on the inverted input signal, the voltage on the first capacitor, and the voltage on the second capacitor.

4. The set and reset pulse generator circuit of claim 2 , wherein the set circuit comprises a first inverter circuit that is configured to charge the first capacitor in accordance with the input signal, the first capacitor, and an And gate that is configured to perform the logical operation to generate the set pulse.

5. The set and reset pulse generator circuit of claim 4 , wherein the reset circuit comprises an inverter buffer that is configured to invert the input signal to generate an inverted input signal, a second capacitor, a second inverter circuit that is configured to charge the second capacitor in accordance with the inverted input signal, and an And gate that is configured to perform a logical And operation on the inverted input signal, the voltage on the first capacitor, and the voltage on the second capacitor to generate the reset pulse.

6. The set and reset pulse generator circuit of claim 5 , wherein the first inverter circuit comprises a first pull-up transistor and a first pull-down transistor that are complementary switched in accordance with the input signal, and the second inverter circuit comprises a second pull-up transistor and a second pull-down transistor that are complementary switched in accordance with the inverted input signal.

7. The set and reset pulse generator circuit of claim 1 , wherein the first cross-coupling circuit comprises a first hysteresis circuit and the second cross-coupling circuit comprises a second hysteresis circuit.

8. The set and reset pulse generator circuit of claim 1 , wherein the first cross-coupling circuit comprises a first delay circuit and the second cross-coupling circuit comprises a second delay circuit.

9. A set and reset pulse generator circuit, comprising:

a first inverter circuit that is configured to receive an input signal, and to control a switching operation of a first transistor pair in accordance with the input signal to charge a first capacitor to generate a first voltage signal;

a second inverter circuit that is configured to control a switching operation of a second transistor pair in accordance with an inverted input signal to charge a second capacitor to generate a second voltage signal;

a first output circuit that is configured to generate a set signal based on the input signal, the first voltage signal, and the second voltage signal;

a second output circuit that is configured to generate a reset signal based on the inverted input signal, the first voltage signal, and the second voltage signal;

a first cross-coupling circuit that is configured to couple the first voltage signal to the second output circuit; and

a second cross-coupling circuit that is configured to couple the second voltage signal to the first output circuit.

10. The set and reset pulse generator circuit of claim 9 , wherein the first cross-coupling circuit comprises a first hysteresis circuit that provides hysteresis to the first voltage signal, and the second cross-coupling circuit comprises a second hysteresis circuit that provides hysteresis to the second voltage signal.

11. The set and reset pulse generator circuit of claim 9 , wherein the first cross-coupling circuit further comprises a first delay circuit that delays the first voltage signal by a first delay value, and wherein the second cross-coupling circuit comprises a second delay circuit that delays the second voltage signal by a second delay value.

12. The set and reset pulse generator circuit of claim 9 , the wherein the first cross-coupling circuit comprises a first buffer circuit, and the second cross-coupling circuit comprises a second buffer circuit.

13. The set and reset pulse generator circuit of claim 9 , wherein the first transistor pair comprises a first pull-up transistor and a first pull-down transistor, and the second transistor pair comprises a second pull-up transistor and a second pull-down transistor.

14. The set and reset pulse generator circuit of claim 13 , wherein the first pull-up transistor is a PMOS transistor and the first pull-down transistor is an NMOS transistor with the first pull-up transistor having a channel width that is wider than a channel width of the first pull-down transistor, and

wherein the second pull-up transistor is a PMOS transistor and the second pull-down transistor is an NMOS transistor with the second pull-up transistor having a channel width that is wider than a channel width of the second pull-down transistor.

15. The set and reset pulse generator circuit of claim 9 , wherein the first output circuit comprises a first And gate that performs a logical And operation on the input signal, the first voltage signal, and the second voltage signal to generate the set signal.

16. The set and reset pulse generator circuit of claim 15 , wherein the second output circuit comprises a second And gate that performs a logical And operation on the inverted input signal, the first voltage signal, and the second voltage signal to generate the reset signal.

17. A method of operating a set and reset pulse generator circuit, the method comprising:

receiving an input signal;

generating a first voltage signal by controlling a switching operation of a first transistor pair in accordance with the input signal to charge a first capacitor that provides the first voltage signal;

inverting the input signal to generate an inverted input signal;

generating a second voltage signal in accordance with the inverted input signal;

generating a set signal based on the input signal, the first voltage signal, and the second voltage signal; and

generating a reset signal that is complementary to the set signal based on the inverted input signal, the first voltage signal, and the second voltage signal.

18. The method of claim 17 , wherein generating the second voltage signal comprises:

controlling a switching operation of a second transistor pair in accordance with the inverted input signal to charge a second capacitor that provides the second voltage signal.

19. The method of claim 18 , wherein the set signal is generated by performing a logical And operation on the input signal, the first voltage signal, and the second voltage signal, and wherein the reset signal is generated by performing a logical And operation on the inverted input signal, the first voltage signal, and the second voltage signal.