Memory devices with improved refreshing operation
A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.
1. A memory device, comprising:
a plurality of memory cells coupled to a bit line, wherein at least one memory cell of the plurality of memory cells is configured to store predetermined data; and
a refresh module configured to refresh the at least one memory cell if a target memory cell of the plurality of memory cells is programmed or erased, to keep at least one cell current of the at least one memory cell at a level different from a predetermined verify current level.
2. The memory device of claim 1 , wherein the refresh module is further configured to read the predetermined data from the at least one memory cell and then rewrite the predetermined data back to the at least one memory cell, to refresh the at least one memory cell.
3. The memory device of claim 1 , wherein if the at least one memory cell is a programmed memory cell, the refresh module is further configured to determine if a current level of the at least one memory cell is lower than a programmed verifying current level.
4. The memory device of claim 3 , wherein the refresh module is further configured to refresh the at least one memory cell if the current level of the at least one memory cell is higher than or equal to the programmed verifying current level.
5. The memory device of claim 1 , wherein if the at least one memory cell is an erased memory cell, the refresh module is further configured to determine if a current level of the at least one memory cell is higher than an erased verifying current level.
6. The memory device of claim 5 , wherein the refresh module is further configured to refresh the at least one memory cell if the current level of the at least one memory cell is lower than or equal to the erased verifying current level.
7. The memory device of claim 1 , further comprising:
a selecting module configured to select the at least one memory cell from the plurality of memory cells to be programmed or erased; and
a processing module configured to apply a selecting voltage to the at least one memory cell, in order to program or erase the at least one memory cell.
8. A memory device, comprising:
a plurality of memory cells coupled to a bit line,
wherein at least one memory cell of the plurality of memory cells is configured to store predetermined data, and the at least one memory cell corresponds to a distribution curve that is associated with a read margin; and
a refresh module configured to refresh the at least one memory cell at least by rewriting the predetermined data to the at least one memory cell, if a target memory cell of the plurality of memory cells is programmed or erased, in order to refrain a width of the distribution curve from expanding.
9. The memory device of claim 8 , wherein if the at least one memory cell is a programmed memory cell, the refresh module is configured to refresh the at least one memory cell if a voltage level of the at least one memory cell is higher than or equal to a predetermined verifying voltage level, or if a current level of the at least one memory cell is higher than or equal to a predetermined verifying current level.
10. The memory device of claim 8 , wherein if the at least one memory cell is an erased memory cell, the refresh module is configured to refresh the at least one memory cell if a voltage level of the at least one memory cell is lower than or equal to a predetermined verifying voltage level, or if a current level of the at least one memory cell is lower than or equal to a predetermined verifying current level.
11. The memory device of claim 8 , further comprising:
a selecting module configured to select the at least one memory cell from the plurality of memory cells to be programmed or erased; and
a processing module configured to apply a selecting voltage to the at least one memory cell, in order to program or erase the at least one memory cell.
12. A method, comprising:
programming or erasing a target memory cell; and
refreshing a memory cell storing predetermined data corresponding to a distribution curve that is associated with a read margin, at least by rewriting the predetermined data to the memory cell, to refrain a width of the distribution curve from expanding,
wherein the memory cell and the target memory cell are associated with a data line.
13. The method of claim 12 , wherein the memory cell and the target memory cell are coupled to a bit line.
14. The method of claim 12 , wherein if the memory cell is a programmed memory cell, refreshing the memory cell comprises:
determining if a voltage level of the memory cell is lower than a predetermined verifying voltage level or a current level of the memory cell is lower than a predetermined verifying current level.
15. The method of claim 14 , wherein the memory cell is refreshed if the voltage level of the memory cell is higher than or equal to the predetermined verifying voltage level, or if the current level of the memory cell is higher than or equal to the predetermined verifying current level.
16. The method of claim 12 , wherein if the memory cell is an erased memory cell, refreshing the memory cell comprises:
determining if a voltage level of the memory cell is higher than a predetermined verifying voltage level or a current level of the memory cell is higher than a predetermined verifying current level.
17. The method of claim 16 , wherein the memory cell is refreshed if the voltage level of the memory cell is lower than or equal to the predetermined verifying voltage level, or if the current level of the memory cell is lower than or equal to the predetermined verifying current level.
18. The method of claim 12 , further comprising initializing an operation count.
19. The method of claim 18 , further comprising:
increasing the operation count if a voltage level of the memory cell is lower than a predetermined verifying voltage level; and
determining if the memory cell is checked in accordance with the operation count.
20. The method of claim 18 , further comprising:
increasing the operation count when a current level of the memory cell is lower than a predetermined verifying current level; and
determining if the memory cell is checked in accordance with the operation count.