Display device
A display device includes a thin film transistor, a gate insulting layer, an interlayer insulating layer, a data line, a spacer, and a pixel. The thin film transistor includes a semiconductor layer and a gate electrode. The semiconductor layer includes a source region and a drain region on respective sides of the channel region. The gate insulating layer is between the semiconductor layer and the gate electrode. The interlayer insulating layer covers the thin film transistor. The data line contacts the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer. The spacer is on an inner wall of the hole and contacting the data line. The pixel electrode is electrically connected to the thin film transistor.
1. A display device, comprising:
a substrate;
a thin film transistor on the substrate and including a semiconductor layer and a gate electrode, the semiconductor layer including a source region and a drain region on respective sides of a channel region;
a gate insulating layer between the semiconductor layer and the gate electrode;
an interlayer insulating layer covering the thin film transistor;
a data line contacting the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer;
a spacer on an inner wall of the hole, contacting the data line, and penetrating into the semiconductor layer; and
a pixel electrode electrically connected to the thin film transistor, wherein:
the semiconductor layer includes a first region, a second region, and a third region, the third region being between the first region and the second region,
the first region contacts the data line and has a thickness less than that of the second region and the third region,
the third region contacts the spacer,
the first region is stepped from the third region, and
a connection portion between the first region and the third region has a forward-tapered slope.
2. The display device as claimed in claim 1 , wherein:
a lower surface of the data line directly contacts one of the source region and the drain region, and
a surface of the data line facing an inner wall of the hole directly contacts the spacer.
3. The display device as claimed in claim 1 , wherein the second region overlaps the gate insulating layer and the interlayer insulating layer.
4. The display device as claimed in claim 1 , wherein the first region and the second region are doped with same impurities.
5. The display device as claimed in claim 1 , wherein the third region has a thickness less than the second region.
6. The display device as claimed in claim 1 , wherein the spacer includes:
a first lateral surface facing the inner wall of the hole, and
a lower surface facing one of the source region or the drain region, wherein the first lateral surface directly contacts the interlayer insulating layer, the gate insulating layer, and the semiconductor layer, and wherein the lower surface directly contacts one of the source region or the drain region.
7. The display device as claimed in claim 1 , wherein the thin film transistor includes:
a driving thin film transistor includes a driving semiconductor layer and a driving gate electrode, the driving semiconductor layer including a driving channel region, a driving source region, and a driving drain region, and the driving gate electrode overlapping the driving channel region; and
a switching thin film transistor over the substrate and including a switching semiconductor layer and a switching gate electrode, the switching semiconductor layer including a switching channel region, a switching source region, and a switching drain region, the switching gate electrode overlapping the switching channel region, and the data line contacting one of the switching source region and the switching drain region.
8. The display device as claimed in claim 7 , wherein the spacer includes metal.
9. The display device as claimed in claim 8 , wherein the spacer includes a same metallic material as the data line.
10. The display device as claimed in claim 1 , further comprising:
a second gate insulating layer between the gate insulating layer and the interlayer insulating layer; and
a first storage capacitor plate facing a second storage capacitor plate with the second gate insulating layer therebetween, the spacer directly contacting the interlayer insulating layer, the second gate insulating layer, the gate insulating layer, and the semiconductor layer.
11. The display device as claimed in claim 1 , wherein the spacer includes an insulating material.
12. The display device as claimed in claim 11 , wherein the insulating material includes at least one of SiOx, SiNx, SiON, or SiOC.
13. The display device as claimed in claim 1 , wherein the spacer partially penetrates the semiconductor layer.
14. A display device, comprising:
a substrate;
a thin film transistor on the substrate and including a semiconductor layer and a gate electrode, the semiconductor layer including a source region and a drain region on respective sides of a channel region;
a gate insulating layer between the semiconductor layer and the gate electrode;
an interlayer insulating layer covering the thin film transistor;
a data line contacting the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer;
a spacer on an inner wall of the hole, contacting the data line, and penetrating into the semiconductor layer; and
a pixel electrode electrically connected to the thin film transistor, wherein the spacer extends to an upper surface of the interlayer insulating layer and directly contacts at least a portion of the upper surface of the interlayer insulating layer.
15. The display device as claimed in claim 14 , wherein the spacer includes an insulating material.
16. The display device as claimed in claim 15 , wherein the insulating material includes at least one of SiOx, SiNx, SiON, or SiOC.
17. The display device as claimed in claim 14 , wherein the spacer partially penetrates the semiconductor layer.
18. A display device, comprising:
a substrate;
a thin film transistor on the substrate and including a semiconductor layer and a gate electrode, the semiconductor layer including a source region and a drain region on respective sides of a channel region;
a gate insulating layer between the semiconductor layer and the gate electrode;
an interlayer insulating layer covering the thin film transistor;
a data line contacting the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer;
a spacer on an inner wall of the hole and contacting the data line; and
a pixel electrode electrically connected to the thin film transistor, wherein:
the semiconductor layer includes a first region, a second region, and a third region, the third region being between the first region and the second region,
the first region contacts the data line and has a thickness less than that of the second region and the third region,
the third region contacts the spacer,
the first region is stepped from the third region, and
a connection portion between the first region and the third region has a forward-tapered slope.
19. A display device, comprising:
a substrate;
a first thin film transistor on the substrate;
a pixel electrode electrically connected to the first thin film transistor,
a second thin film transistor on the substrate and including a semiconductor layer and a gate electrode, the semiconductor layer including a source region and a drain region on respective sides of a channel region;
a gate insulating layer between the semiconductor layer and the gate electrode;
an interlayer insulating layer covering the thin film transistor;
a data line disposed between the substrate and the pixel electrode, and contacting the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer; and
a spacer on an inner wall of the hole and contacting the data line;
wherein the spacer extends to an upper surface of the interlayer insulating layer and directly contacts at least a portion of the upper surface of the interlayer insulating layer.