Semiconductor device including trimmed-gates and method for generating layout of same

1. A method of generating a layout of a semiconductor device, the layout being stored on a non-transitory computer-readable medium, the method comprising:

generating active area (AR) patterns arranged in a first grid oriented parallel to a first direction;

generating gate patterns arranged spaced apart in a second grid and overlying corresponding ones of the AR patterns, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction;

wherein gaps, which are interspersed between neighboring ones of the AR patterns, are overlied by corresponding intra-gap segments of the gate patterns, each intra-gap segment including two end regions separated by a central region;

generating first cut-patterns which overlie the central regions of first selected ones of the intra-gap segments; and

generating second cut-patterns which overlie the end regions of second selected ones of the intra-gap segments which abut flyover intersections thereby trimming the corresponding gate patterns;

wherein:

the first and second cut-patterns are indicative that corresponding underlying central regions and end regions will be removed subsequently;

each of the flyover intersections is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be not be functionally connected to an active region resulting from the corresponding AR pattern; and

at least one of the generating AR patterns, generating gate patterns, generating first cut-patterns or generating second cut-patterns is executed by a processor of a computer.

2. The method of claim 1 , further comprising:

fabricating, based on the layout, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit.

3. The method of claim 1 , wherein:

each gap, central region and end region has a corresponding height in the second direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern;

determination of the height of the first cut-patterns sets the height of the central regions of the intra-gap segments of the gate patterns and consequently sets the heights of end regions of the intra-gap segments of the gate patterns; and

the generating first cut-patterns includes:

setting the height of the first cut-patterns such that, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, a consequential height of the end regions is sufficient to ensure that gate electrodes resulting from corresponding gate patterns will extend a predetermined distance in the second direction beyond the functional intersections.

4. The method of claim 3 , wherein the setting the height of the first cut-patterns includes:

choosing the height of the first cut-patterns such that the consequential height of the end regions H EXT is less than or equal to about a three times multiple of a width W G in the first direction of the gate patterns, wherein:

H EXT ≤(≈3 W G ).

5. The method of claim 1 , wherein:

each gate pattern and second cut-pattern has a corresponding width in the first direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern; and

the generating second cut-patterns includes:

setting the width of the second cut-patterns, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, to be a predetermined size which is greater than the width of corresponding gate patterns.

6. The method of claim 5 , wherein the setting the width of the second cut-patterns includes:

the width of the gate patterns is referred to as W G ;

the width of the second cut-patterns is referred to as W CP2 ; and

choosing the width of the second cut-patterns W CP2 to be less than or equal to about a 12 times multiple of a width W G of the gate patterns, wherein:

W CP2 ≤(≈12 W G ).

7. The method of claim 1 , wherein the generating second cut-patterns further includes:

substantially aligning, relative to the first direction, midlines of the second cut-patterns over centerlines of the corresponding gate patterns.

8. The method of claim 1 , wherein the generating AR patterns includes:

configuring the AR patterns for finFET technology.

9. A non-transitory, computer-readable medium comprising computer-executable instructions for carrying out a method of generating a layout of a semiconductor device, the method comprising:

generating active area (AR) patterns arranged in a first grid oriented parallel to a first direction;

generating gate patterns arranged spaced apart in a second grid and overlying corresponding ones of the AR patterns, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction;

wherein gaps, which are interspersed between neighboring ones of the AR patterns, are overlied by corresponding intra-gap segments of the gate patterns, each intra-gap segment including two end regions separated by a central region;

generating first cut-patterns which overlie the central regions of first selected ones of the intra-gap segments; and

generating second cut-patterns which overlie the end regions of second selected ones of the intra-gap segments which abut flyover intersections thereby trimming the corresponding gate patterns;

wherein:

the first and second cut-patterns are indicative that corresponding underlying central regions and end regions will be removed subsequently; and

each of the flyover intersections is an instance of an intersection at which a corresponding gate pattern intersects a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be not be functionally connected to an active region resulting from the corresponding AR pattern.

10. The computer-readable medium of claim 9 , wherein the method further comprises:

controlling a semiconductor fabrication process to fabricate, based on the layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

11. The computer-readable medium of claim 9 , wherein:

each gap, central region and end region has a corresponding height in the second direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern intersects a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern;

determination of the height of the first cut-patterns sets the height of the central regions of the intra-gap segments of the gate patterns and consequently sets the heights of end regions of the intra-gap segments of the gate patterns; and

the generating first cut-patterns includes:

setting the height of the first cut-patterns such that, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, a consequential height of the end regions is sufficient to ensure that gate electrodes resulting from corresponding gate patterns will extend a predetermined distance in the second direction beyond the functional intersections.

12. The computer-readable medium of claim 11 , wherein the setting the height of the first cut-patterns includes:

choosing the height of the first cut-patterns such that the consequential height of the end regions H EXT is less than or equal to about a three times multiple of a width W G in the first direction of the gate patterns, wherein:

H EXT ≤(≈3 W G ).

13. The computer-readable medium of claim 9 , wherein:

each gate pattern and second cut-pattern has a corresponding width in the first direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern intersects a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern; and

the generating second cut-patterns includes:

setting the width of the second cut-patterns, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, to be a predetermined size which is greater than the width of corresponding gate patterns.

14. The computer-readable medium of claim 13 , wherein the setting the width of the second cut-patterns includes:

the width of the gate patterns is referred to as W G ;

the width of the second cut-patterns is referred to as W CP2 ; and

choosing the width of the second cut-patterns W CP2 to be less than or equal to about a 12 times multiple of a width W G , of the gate patterns, wherein:

W CP2 ≤(≈12 W G ).

15. The computer-readable medium of claim 13 , wherein the generating second cut-patterns further includes:

substantially aligning, relative to the first direction, midlines of the second cut-patterns over centerlines of the corresponding gate patterns.

16. The computer-readable medium of claim 9 , wherein the generating AR patterns includes:

configuring the AR patterns for finFET technology.

17. A method of generating a layout of a semiconductor device , the layout being stored on a non-transitory computer-readable medium, the method comprising:

generating active area (AR) patterns arranged in a first grid oriented parallel to a first direction;

generating gate patterns arranged spaced apart in a second grid and overlying corresponding ones of the AR patterns, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction;

wherein gaps, which are interspersed between neighboring ones of the AR patterns, are overlied by corresponding intra-gap segments of the gate patterns, each intra-gap segment including two end regions separated by a central region;

generating first cut-patterns which overlie the central regions of first selected ones of the intra-gap segments;

generating second cut-patterns which overlie the end regions of second selected ones of the intra-gap segments which abut flyover intersections thereby trimming the corresponding gate patterns;

substantially aligning, relative to the first direction, midlines of the second cut-patterns over centerlines of the corresponding gate patterns; and

wherein:

the first and second cut-patterns are indicative that corresponding underlying central regions and end regions will be removed subsequently;

each of the flyover intersections is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be not be functionally connected to an active region resulting from the corresponding AR pattern; and

at least one of the generating AR patterns, generating gate patterns, generating first cut-patterns or generating second cut-patterns is executed by a processor of a computer.

18. The method of claim 17 , further comprising:

fabricating, based on the layout, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit.

19. The method of claim 17 , wherein:

each gap, central region and end region has a corresponding height in the second direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern;

determination of the height of the first cut-patterns sets the height of the central regions of the intra-gap segments of the gate patterns and consequently sets the heights of end regions of the intra-gap segments of the gate patterns; and

the generating first cut-patterns includes:

setting the height of the first cut-patterns such that, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, a consequential height of the end regions is sufficient to ensure that gate electrodes resulting from corresponding gate patterns will extend a predetermined distance in the second direction beyond the functional intersections.

20. The method of claim 17 , wherein:

each gate pattern and second cut-pattern has a corresponding width in the first direction;

a functional intersection is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be functionally connected to an active region resulting from the corresponding AR pattern; and

the generating second cut-patterns includes:

setting the width of the second cut-patterns, for corresponding ones of the end regions of the intra-gap segments which abut functional intersections, to be a predetermined size which is greater than the width of corresponding gate patterns.