Nanosheet semiconductor structure with inner spacer formed by oxidation
A method for fabricating a semiconductor structure includes forming a nanosheet stack on a base. The nanosheet stack comprises one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material. The nanosheet stack is recessed. Inner spacers comprising a third material are formed. Forming the inner spacers includes converting the first material corresponding to outer portions of each of the one or more first nanosheet layers into the third material.
1. A method for fabricating a semiconductor structure, the method comprising:
forming a nanosheet stack on a base, wherein the nanosheet stack comprises one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material;
recessing the nanosheet stack; and
forming inner spacers comprising a third material, wherein forming the inner spacers comprises converting the first material corresponding to outer portions of each of the one or more first nanosheet layers into the third material, wherein a length of the one or more second nanosheet layers exceed a length of the inner spacers.
2. The method of claim 1 , wherein converting the outer portions of the one or more first nanosheet layers into the inner spacers comprises selectively oxidizing the first material.
3. The method of claim 2 , wherein the selective oxidation is performed utilizing low-temperature oxidation.
4. The method of claim 3 , wherein the selective oxidation is performed utilizing water vapor oxidation at a temperature of around 350 degrees Celsius.
5. The method of claim 1 , wherein the inner spacers have a lateral thickness less than a lateral thickness of the first nanosheet layers, thereby causing the second nanosheet layers to extend beyond the inner spacers.
6. The method of claim 1 , wherein at least one of the first material and the second material is comprised of a III-V compound.
7. The method of claim 6 , wherein the first material is comprised of aluminum gallium arsenide, and wherein the second material is comprised of one of gallium arsenide and indium gallium arsenide.
8. The method of claim 7 , wherein the third material is comprised of aluminum oxide.
9. The method of claim 1 , further comprising forming at least one interlayer dielectric and at least one source/drain region after the conversion step.
10. The method of claim 1 , further comprising forming a cladding spacer and a dummy gate around the nanosheet stack prior to recessing the nanosheet stack.
11. The method of claim 10 , further comprising selectively removing the dummy gate and the one or more first nanosheet layers.
12. The method of claim 11 , further comprising forming a replacement metal gate, and forming at least one contact within the at least one interlayer dielectric and in contact with the at least one source/drain region.
13. The method of claim 12 , further comprising forming a gate dielectric layer prior to forming the replacement metal gate.
14. The method of claim 1 , wherein the nanosheet stack is recessed using a dry etching process.
15. The method of claim 14 , wherein the dry etching process used to recess the nanosheet stack is reactive-ion etching.
16. The method of claim 1 , wherein the base comprises a substrate and a buffer formed on the substrate.
17. The method of claim 16 , wherein the substrate is comprised of silicon, and wherein the buffer is comprised of a III-V compound.
18. The method of claim 17 , wherein the III-V compound is gallium arsenide phosphide.
19. The method of claim 1 , wherein the first material comprises aluminum gallium arsenide and the third material of the inner spacer comprises aluminum oxide (Al 2 O 3 ).
20. The method of claim 9 , wherein the at least one source/drain region is epitaxially grown.