Power on reset circuit

1. A power on reset circuit, comprising:

a threshold level control circuit configured to set threshold level values during power on reset and power off reset operations;

a capacitor charge and discharge circuit connected to the threshold level control circuit and configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and

a current bias circuit configured to provide a reference current not varying with a power supply coupled to the threshold level control circuit and the capacitor charge and discharge circuit, the current bias circuit comprising:

a first reference current output terminal connected to the threshold level control circuit;

a second reference current output terminal connected to the capacitor charge and discharge circuit; and

a third reference current output terminal connected to the capacitor charge and discharge circuit.

2. The power on reset circuit of claim 1 , wherein the current bias circuit comprises: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a sixth field effect transistor; wherein a gate of the first field effect transistor is connected to a drain thereof; the drain of the first field effect transistor is externally connected to a reference current source; sources of the first field effect transistor, the second field effect transistor and the third field effect transistor are grounded; a gate of the second field effect transistor is connected to the gate of the first field effect transistor; a drain of the second field effect transistor is connected to a drain of the fourth field effect transistor; a gate of the third field effect transistor is connected to the gate of the first field effect transistor; a drain of the third field effect transistor serves as the third reference current output terminal; sources of the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are connected to the power supply; a gate of the fourth field effect transistor is connected to a drain thereof and gates of the fifth field effect transistor and the sixth field effect transistor; a drain of the fifth field effect transistor serves as the second reference current output terminal; and a drain of the sixth field effect transistor serves as the first reference current output terminal.

3. The power on reset circuit of claim 2 , wherein the first field effect transistor, the second field effect transistor and the third field effect transistor are N-type field effect transistors; the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are P-type field effect transistors.

4. The power on reset circuit of claim 1 , wherein the threshold level control circuit comprises a first diode and a second diode connected in series; wherein an anode of the first diode is connected to the first reference current output terminal; a cathode of the first diode is connected to an anode of the second diode; and a cathode of the second diode is grounded.

5. The power on reset circuit of claim 4 , wherein the threshold level control circuit further comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third diode, a first comparator, a second comparator, a third comparator, a first NOR gate and a second NOR gate; wherein, the first resistor, the second resistor and the third resistor are connected in series between the first reference current output terminal and the ground; the fourth resistor, the fifth resistor and the sixth resistor are connected in series between the power supply and the ground;

a non-inverting input terminal of the first comparator is connected between the fourth resistor and the fifth resistor; an inverting input terminal of the first comparator is connected between the first resistor and the second resistor; an output terminal of the first comparator is connected to a first input terminal of the first NOR gate;

a non-inverting input terminal of the second comparator is connected between the second resistor and the third resistor; an inverting input terminal of the second comparator is connected between the fourth resistor and the fifth resistor; an output terminal of the second comparator is connected to a first input terminal of the second NOR gate;

a non-inverting input terminal of the third comparator is connected to the first reference current output terminal; an inverting input terminal of the third comparator is connected between the fifth resistor and the sixth resistor; an output terminal of the third comparator is connected to the capacitor charge and discharge circuit;

the third diode is connected between the inverting input terminal of the third comparator and the ground;

an output terminal of the first NOR gate is connected to a second input terminal of the second NOR gate; an output terminal of the second NOR gate is connected to a second input terminal of the first NOR gate and the capacitor charge and discharge circuit.

6. The power on reset circuit of claim 1 , wherein the capacitor charge and discharge circuit comprises: a seventh field effect transistor, a eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, a first capacitor and an inverter; wherein

a source of the seventh field effect transistor is connected to the power supply; a drain of the seventh field effect transistor is connected to a drain of the eighth field effect transistor, a drain of the ninth field effect transistor, a gate of the tenth field effect transistor, an anode of the first capacitor and an input terminal of the inverter respectively; sources of the eighth field effect transistor and the ninth field effect transistor are connected to the second reference current output terminal and the third reference current output terminal respectively; a source and a drain of the tenth field effect transistor and a cathode of the first capacitor are grounded; and an output of the inverter outputs the power on reset signal.

7. The power on reset circuit of claim 6 , wherein the seventh field effect transistor and the eighth field effect transistor are P-type field effect transistors; the ninth field effect transistor and tenth field effect transistor are N-type field effect transistors.

8. The power on reset circuit of claim 6 , wherein the first capacitor is a MIM capacitor.

9. The power on reset circuit of claim 1 , wherein a current value output by the second reference current output terminal is an integer multiple of a current value output by the third reference current output terminal.

10. The power on reset circuit of claim 9 , wherein the current value output by the second reference current output terminal is the double of the current value output by the third reference current output terminal.