IP Library Granted Patent US 10,396,001
Granted Patent B2
US 10,396,001 · App. 15/737,470 · Granted Aug 27, 2019

Offset test pads for WLCSP final test

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Quick Facts
Patent No.
US 10,396,001
App. No.
15/737,470
Granted
Aug 27, 2019
Kind
B2
Abstract

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.

Claims (42)

1. A device configured for wafer level chip scale packaging (WLCSP), the device comprising:

a) a first pad;

b) a test pad offset from the first pad;

c) a first redistribution layer (RDL) path that connects the first pad to the test pad with no other pad connections therebetween; and

d) a second RDL path that connects the test pad to a solder ball.

2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.

3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.

4. The device of claim 1 , wherein the first and second RDL paths are in different layers.

5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad, and leaves a portion of the test pad exposed.

6. The device of claim 1 , wherein the device further comprises:

a) a plurality of the first pads; and

b) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.

7. A device configured for WLCSP, the device comprising:

a) a first pad;

b) a test pad offset from the first pad;

c) a first RDL path that connects the first pad to a solder ball; and

d) a second RDL path that connects the test pad to the solder ball,

e) wherein a length of the offset is substantially greater than a diameter of the solder ball.

8. The device of claim 7 , wherein the device comprises a serial NVM device.

9. The device of claim 7 , wherein the first and second RDL paths are in a same layer.

10. The device of claim 7 , wherein the first and second RDL paths are in different layers.

11. The device of claim 7 , further comprising a polymer layer that fully covers the first pad, and leaves a portion of the test pad exposed.

12. The device of claim 7 , wherein the device further comprises:

a) a plurality of the first pads; and

b) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.

13. A wafer comprising the device of claim 7 , the wafer comprising:

a) a first semiconductor device comprising the first pad; and

b) a second semiconductor device comprising the test pad.

14. The wafer of claim 13 , wherein each of the first and second semiconductor devices comprises a serial NVM device.

15. A device configured for WLCSP, the device comprising:

a) a first pad;

b) a test pad offset from the first pad;

c) a first RDL path that connects the first pad to a solder ball; and

d) a second RDL path that connects the test pad to the solder ball,

e) wherein a length of the offset is about a diameter of the solder ball.

16. The device of claim 15 , wherein the device comprises a serial NVM device.

17. The device of claim 15 , wherein the first and second RDL paths are in a same layer.

18. The device of claim 15 , wherein the first and second RDL paths are in different layers.

19. The device of claim 15 , further comprising a polymer layer that fully covers the first pad, and leaves a portion of the test pad exposed.

20. The device of claim 15 , wherein the device further comprises:

a) a plurality of the first pads; and

b) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2017
From: PEDERSEN, BARD M.
To: ADESTO TECHNOLOGIES CORPORATION
Reel/Frame 044421/0518 →