Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
View Patent ↗Some embodiments are directed to the design and manufacture of integrated circuits, and more particularly, some embodiments are directed to the electrical modeling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, some embodiments are directed to the modeling of substrate coupling effects in these circuits.
1. A method for generating an electrical circuit that includes at least a network of diodes, resistors and/or homojunctions, the electrical circuit modelling parasitic effects in a substrate of an integrated circuit that includes electronic devices, the integrated circuit being defined by a set of mask layer layouts and a technology rules file, the method comprising:
generating a simplified 3D layout of the integrated circuit from the set of mask layer layouts and the technology rules file by using only mask layers associated to technology layers involved in the parasitic effects;
defining in the 3D simplified layout a plurality of internal regions, each internal region corresponding to one electronic device of the integrated circuit and one external region corresponding to the part of the simplified 3D layout not included in any internal region;
computing in parallel and independently:
for each internal region, a 3D matrix of adjacent rectangular cuboids, such that there is a limit between at least two adjacent rectangular cuboids where there is a change of doping type or where there is a change of doping concentration in the simplified layout;
for the external region, a mesh of adjacent rectangular cuboids with no overlap and no gap;
extracting a parasitic component with two terminals between each pair of adjacent cuboids, each terminal being positioned at the center of one of the two adjacent cuboids, wherein:
if the two adjacent cuboids have two different doping types, defining the parasitic component as a diode; or
if the two adjacent cuboids have the same doping type with the same doping concentration, defining the parasitic component as a resistor; or
if the two adjacent cuboids have the same doping type and different concentrations, defining the parasitic component as a homojunction; and
defining the electrical characteristics of each parasitic component based on the geometry of the adjacent cuboids and the technological parameters;
connecting all extracted parasitic components into an electrical circuit by considering each rectangular cuboid center as a node of the parasitic component network;
applying a set of xyz coordinates onto the simplified 3D layout, where x and y coordinates define horizontal planes and z coordinate define the integrated circuit depth; and
computing the 3D matrix of internal region by:
scanning the mask layers for finding and collecting corner points of change in the doping type or the doping concentration;
flattening corner points to xy coordinates so that an horizontal rectangular tessellation is built in which each corner point is a corner of at least one rectangle; and
constructing layers of rectangular cuboids by projecting the rectangular tessellation on the z axis, each layer depth corresponding to the depth of at least one corner point.
2. The method according to claim 1 , wherein the mask layer layouts used to generate the simplified 3D layout comprise at least the doped substrate layers and the doped contact layers.
3. The method according to claim 2 , wherein a set of xyz coordinates is applied onto the simplified 3D layout, where x and y coordinates define horizontal planes and z coordinate define the integrated circuit depth.
4. The method according to claim 1 , wherein the internal regions are defined by:
scanning and detecting the outermost area of each internal regions;
collecting the lower left and upper right corner points of each internal regions; and
defining rectangular cuboid with the lower left and upper right corner points as internal region.
5. The method according to claim 4 , wherein, for the external region, the mesh of rectangular cuboids is computed by:
flattening the lower left and upper right corner points of each internal region onto a xy plane;
building a rectangular tessellation in which each corner point is a corner of at least one rectangular cell;
if a rectangular cell is contained inside any one of the internal region area, flag it as “in region” and do nothing; and
if not, verify if the rectangular cell can be merged with an adjacent rectangular cell for forming a merged rectangular cell.
6. A digital data storage medium encoding a machine-executable program of instructions to perform the method according to claim 1 .
7. The method according to claim 1 , wherein the internal regions are defined by:
scanning and detecting the outermost area of each internal regions;
collecting the lower left and upper right corner points of each internal regions; and
defining rectangular cuboid with the lower left and upper right corner points as internal region.
8. A system for generating an electrical circuit that includes at least a network of diodes, resistors and/or homojunctions, the electrical circuit modelling parasitic effects in a substrate of an integrated circuit that includes electronic devices, the integrated circuit being defined by a set of mask layer layouts and a technology rules file, the system comprising:
a generator of a simplified 3D layout of the integrated circuit from the set of mask layer layouts and the technology rules file by using only mask layers associated to technology layers involved in the parasitic effects;
means for defining in the simplified 3D layout a plurality of internal regions, each internal region corresponding to one electronic device of the integrated circuit and one external region corresponding to the part of the simplified 3D layout not included in any internal region;
a computer to compute in parallel and independently:
for each internal region, a 3D matrix of adjacent rectangular cuboids, such that there is a limit between at least two adjacent rectangular cuboids where there is a change of doping type or where there is a change of doping concentration in the simplified layout;
for the external region, a mesh of adjacent rectangular cuboids with no overlap and no gap; and
an extractor of a parasitic component with two terminals between each pair of adjacent cuboids, each terminal being positioned at the center of one of the two adjacent cuboids, wherein:
if the two adjacent cuboids have two different doping types, defining the parasitic component as a diode; or
if the two adjacent cuboids have the same doping type with the same doping concentration, defining the parasitic component as a resistor; or
if the two adjacent cuboids have the same doping type and different concentrations, defining the parasitic component as a homojunction; and
defining the electrical characteristics of each parasitic component based on the geometry of the adjacent cuboids and the technological parameters; and
a network generator of all extracted parasitic components into an electrical circuit by considering each rectangular cuboid center as a node of the parasitic component network
the computer being further configured to cause the system to perform the following:
applying a set of xyz coordinates onto the simplified 3D layout, where x and y coordinates define horizontal planes and z coordinate define the integrated circuit depth;
computing the 3D matrix of internal region by:
scanning the mask layers for finding and collecting corner points of change in the doping type or the doping concentration;
flattening corner points to xy coordinates so that an horizontal rectangular tessellation is built in which each corner point is a corner of at least one rectangle; and
constructing layers of rectangular cuboids by projecting the rectangular tessellation on the z axis, each layer depth corresponding to the depth of at least one corner point.