Array substrate and display device
The application discloses an array substrate and a display device, and belongs to the field of display technology. The array substrate comprises a base substrate, and a via hole and a diffusion part above the base substrate, and an orthographic projection of the diffusion part on the base substrate is contiguous to that of the via hole on the base substrate. The diffusion part is used for causing alignment liquid at a position corresponding to the via hole to diffuse. Since the array substrate is provided with the diffusion part for causing alignment liquid at a position corresponding to the via hole to diffuse, and the orthographic projection of the diffusion part on the base substrate is contiguous to that of the via hole on the base substrate, the alignment liquid at the position corresponding to the via hole will be guided by the diffusion part to diffuse uniformly.
1. An array substrate, comprising a base substrate and a via hole above the base substrate, wherein the array substrate further comprises a diffusion part for causing alignment liquid at a position corresponding to the via hole to diffuse, and an orthographic projection of the diffusion part on the base substrate is contiguous to that of the via hole on the base substrate,
the array substrate further comprises a thin film transistor on the base substrate, a planarization layer above the thin film transistor, and a pixel electrode above the planarization layer;
the via hole is provided in the planarization layer at a position corresponding to a drain of the thin film transistor, and is used for electrically connecting the drain of the thin film transistor to the pixel electrode; and
the diffusion part is a recess in the pixel electrode.
2. The array substrate of claim 1 , wherein a depth of the recess is equal to a thickness of the pixel electrode.
3. The array substrate of claim 1 , wherein a shape of the recess is a rectangle.
4. The array substrate of claim 3 , wherein a length of the recess ranges from nm to 20 μm, and a width of the recess ranges from 1 μm to 100 μm.
5. A display device, comprising the array substrate of claim 1 .
6. The display device of claim 5 , wherein a depth of the recess is equal to a thickness of the pixel electrode.
7. The display device of claim 5 , wherein a shape of the recess is a rectangle.
8. The display device of claim 7 , wherein a length of the recess is in the range of 1 μm to 20 μm, and a width of the recess is in the range of 1 μm to 100 μm.
9. An array substrate, comprising a base substrate and a via hole above the base substrate, wherein the array substrate further comprises a diffusion part for causing alignment liquid at a position corresponding to the via hole to diffuse, and an orthographic projection of the diffusion part on the base substrate is continuous to that of the via hole on the base substrate,
the array substrate further comprises a thin film transistor on the base substrate, a planarization layer above the thin film transistor, and a pixel electrode above the planarization layer;
the via hole is provided in the planarization layer at a position corresponding to a drain of the thin film transistor, and is used for electrically connecting the drain of the thin film transistor to the pixel electrode;
the diffusion pan is a concave in the planarization layer;
a shape of the concave is a rectangle; and
a length of the concave ranges from 1 μm to 20 μm, and a width of the concave ranges from 1 μm to 500 μm.
10. A manufacturing method of an array substrate, comprising a step of forming a via hole above a base substrate, wherein the manufacturing method further comprises a step of forming a diffusion part for causing alignment liquid at a position corresponding to the via hole to diffuse; and wherein an orthographic projection of the diffusion part on the base substrate is contiguous to that of the via hole on the base substrate,
wherein the manufacturing method specifically comprises steps of:
forming a thin film transistor on the base substrate by a patterning process;
forming a planarization layer, and forming a pattern comprising the via hole in the planarization layer at a position corresponding to a drain of the thin film transistor by a patterning process; and
forming a pattern comprising a pixel electrode and the diffusion part by a single patterning process such that the pixel electrode is electrically connected to the drain of the thin film transistor through the via hole, and the diffusion part is a recess in the pixel electrode.