Data sensing in crosspoint memory structures
A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
1. A data storage device, comprising
a memory cell array; and
sense circuitry to detect a data value stored to a memory cell of the memory cell array;
the controller to bias the sense circuitry during a read phase of a write operation;
wherein:
the sense circuitry is to sample a sneak current and subtract the sneak current from the current measured through the memory cell; and
to bias the sense circuitry, the sneak current is further increased or decreased compared the sampled sneak current.
2. The data storage device of claim 1 , wherein to bias the sense circuitry, a reference current is selected based in part on whether a zero or a one is being written to the memory cell.
3. The data storage device of claim 1 , wherein to bias the sense circuitry the sense circuitry is to select a drive voltage to be applied to the memory cell, wherein the selected drive voltage is to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
4. The data storage device of claim 1 , wherein during the write verify phase of a write operation, a plurality measurements are made of the current through the memory cell for different values of a current reference, a drive voltage, and a sneak current.
5. A method of reading a memory cell, comprising:
determining whether a write operation or a read operation is being performed;
selecting a current reference based in part on whether a write operation or a read operation is being performed;
measuring a current through the memory cell and comparing the current to the selected reference current to determine a resistance state of the memory cell;
sampling a sneak current that is to be subtracted from the current measured through the memory cell; and
selecting a sneak current adjustment based in part on whether a write operation or a read operation is being performed;
wherein, if the reading is being performed for a verify phase of a write operation, the selected current reference increases the probability of detecting a value opposite from the value being written to the memory cell.
6. The method of claim 5 , wherein the selected reference current is selected based in part on whether a zero or a one is being written to the memory cell.
7. The method of claim 5 , comprising selecting a drive voltage to drive current through the memory cell to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
8. The method of claim 5 , comprising during a single write verify phase, performing a plurality of measurements of the current through the memory cell using different selections for the current reference, a drive voltage, and a sneak current.
9. A data storage device comprising circuitry to:
determine whether a write operation or a read operation is being performed;
select a current reference based in part on whether a write operation or a read operation is being performed; and
measure a current through the memory cell and comparing the current to the selected reference current to determine a resistance state of the memory cell;
wherein, if the reading is being performed for a verify phase of a write operation, the selected current reference increases the probability of detecting a value opposite from the value being written to the memory cell.
10. The data storage device of claim 9 , wherein the selected reference current is selected based in part on whether a zero or a one is being written to the memory cell.
11. The data storage device of claim 9 , comprising selecting a drive voltage to drive current through the memory cell that is different from the first drive voltage and increases the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
12. The data storage device of claim 9 , comprising sampling a sneak current that is to be subtracted from the current measured through the memory cell, and selecting a sneak current adjustment based in part on whether a write operation or a read operation is being performed.
13. The data storage device of claim 9 , comprising during a single write verify phase, performing several measurements of the current through the memory cell using different selections for the current reference, a drive voltage, and a sneak current.