Mixed hardware and software instructions for cryptographic functionalities implementation

1. A device having a central processing unit, RAM memory and at least two hardware specific elementary set of instructions, called hardware elementary operations, using registers, wherein each of the registers is of greater capacity size than the one of the central processing unit, said hardware elementary operations having inputs/outputs/intermediary data compatible with masking, said device being such that:

construction of at least one part of the RAM memory is managed only by the hardware elementary operations and independent of the central processing unit, wherein the RAM memory comprises sensible randomized tables used by software instructions to execute at least a cryptographic functionality in a secure way without any values leakage,

said hardware elementary operations themselves and masking of inputs/outputs/intermediary data are monitored by said software instructions,

said software instructions being able to address different cryptographic functionalities using said hardware elementary operations according to several ways depending on each concerned functionality, said software instructions being further able to address several levels of security in the execution of the different functionalities.

2. The device according to claim 1 , wherein at least one hardware elementary operation is present in several cryptographic functionalities.

3. The device according to claim 1 , wherein said hardware elementary operations implement, for their execution, rapid dedicated RAM access devoid of interaction with the central processing unit.

4. The device according to claim 3 , wherein the rapid dedicated RAM access is used for randomization of substitution tables.

5. The device according to claim 1 , wherein said hardware elementary operations are chosen among: EXCH, MOV, XNOR, TEST_ZERO, SLL, SRL, ROTL, ROTL, XOR, AND, OR, ADD, SET_PERMUT_SEED, INIT_PERMUT_COUNT, GEN_PERMUT, WR_RAM8, WR_RAM4H, WR_RAM4L, ARITH2BOOL, BOOL2ARITH, AES_SHIFTROWL, SHIFTROWH, AES_MIXCOL64, AES_SUBBYTE32L, AES_SUBBYTE32H, AES_INVSHIFTROWL, AES_INVSHIFTROWH, AES_INVMIXCOL64, AES_INVSUBBYTE32L, AES_INVSUBBYTE32H, AES_SBOX_RAM, DES_LOAD_KEY, DES_KEYSCHEDULE_ENC, DES_KEYSCHEDULE_DEC, DES_PC2, DES_INITPERM, DES_FINALPERM, DES_EXPAND, DES_PERMUTE, DES_SBOX, DES_SBOX_RAM, DES_KEY_PACK, DES_KEY_UNPACK, MULT_2_128.

6. A method to implement different cryptographic functionalities in a device having a central processing unit, RAM memory and at least two hardware specific elementary set of instructions, called hardware elementary operations, using registers, wherein each of the registers is of greater capacity size than the one of the central processing unit, said hardware elementary operations having inputs/outputs/intermediary data compatible with masking, said method comprising the steps of:

managing at least one part of the RAM memory only by the hardware elementary operations and independent of the central processing unit, wherein the RAM memory comprises sensible randomized tables used by software instructions to execute at least a cryptographic functionality in a secure way without any values leakage,

developing said software instructions to monitor hardware elementary operations and masking of inputs/outputs/intermediary data, said software instructions being able to address the different cryptographic functionalities using said hardware elementary operations according to several ways depending on each concerned functionality,

customizing software instructions to address several levels of security in the execution of the different functionalities, and

storing the obtained software instructions for further execution of the cryptographic functionalities.