Optoelectronic semiconductor chip and method for producing same
An optoelectronic semiconductor chip ( 10 ) is specified, comprising a p-type semiconductor region ( 4 ), an n-type semiconductor region ( 6 ), and an active layer arranged between the p-type semiconductor region ( 4 ) and the n-type semiconductor region ( 6 ), said active layer being designed as a multiple quantum well structure ( 5 ), wherein the multiple quantum well structure ( 5 ) comprises quantum well layers ( 53 ) and barrier layers ( 51 ), wherein the barrier layers ( 51 ) are doped, and wherein undoped intermediate layers ( 52, 54 ) are arranged between the quantum well layers ( 53 ) and the barrier layers ( 51 ). Furthermore, a method for producing the optoelectronic semiconductor chip ( 10 ) is specified.
1. A method for producing an optoelectronic semiconductor chip, comprising an epitaxial growth of a semiconductor layer sequence having a p-type semiconductor region, an n-type semiconductor region and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, said active layer being in the form of a multi-quantum-well structure, wherein
the multi-quantum-well structure comprises quantum-well layers and barrier layers,
the barrier layers are doped,
undoped intermediate layers are arranged between the quantum-well layers and the barrier layers, and
the undoped intermediate layers are grown at a higher growth temperature than the doped barrier layers, wherein
the barrier layers comprise Al m1 Ga 1-m1 As n1 P 1-n1 with O≤n1≤1,
the undoped intermediate layers comprise Al m2 Ga 1-m2 As n2 P 1-n2 with O≤m2≤1 and O≤n2≤1, and
wherein |m1−m2|≤0.1 and |n1−n2|≤0.1.
2. The method according to claim 1 ,
wherein the growth temperature during the growth of the undoped intermediate layers is at least 650° C.
3. The method according to claim 1 ,
wherein the growth temperature during the growth of the barrier layers is less than 600° C.
4. An optoelectronic semiconductor chip, comprising:
a p-type semiconductor region,
an n-type semiconductor region,
an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, said active layer being in the form of a multi-quantum-well structure, wherein
the multi-quantum-well structure comprises quantum-well layers and barrier layers,
the barrier layers are doped, and
undoped intermediate layers are arranged between the quantum-well layers and the barrier layers, wherein
the barrier layers comprise Al m1 Ga 1-m1 As n1 P 1-n1 with 0≤m1≤1 and 0≤n1≤1,
the undoped intermediate layers comprise Al m2 Ga 1-m2 As n2 P 1-n2 with 0≤m2≤1 and 0≤n2≤1, and
wherein |m1−m2|≤0.1 and |n1−n2|≤0.1.
5. The optoelectronic semiconductor chip according to claim 4 , wherein the quantum-well layers each adjoin undoped intermediate layers on both sides.
6. The optoelectronic semiconductor chip according to claim 4 , wherein the undoped intermediate layers are between 1 nm and 10 nm thick.
7. The optoelectronic semiconductor chip according to claim 4 , wherein the undoped intermediate layers are less than 3 nm thick.
8. The optoelectronic semiconductor chip according to claim 4 , wherein the undoped intermediate layers are thinner than the barrier layers.
9. The optoelectronic semiconductor chip according to claim 4 , wherein the quantum-well layers comprise In x Al y Ga 1-x-y As with 0≤x≤1, 0≤y≤1 and x+y≤1.
10. The optoelectronic semiconductor chip according to claim 4 , wherein n2=1.
11. The optoelectronic semiconductor chip according to claim 4 , wherein an electronic band gap of the undoped intermediate layers differs by no more than 0.1 eV from the electronic band gap of the barrier layers.
12. The optoelectronic semiconductor chip according to claim 4 , wherein the barrier layers have the same material composition as the undoped intermediate layers, apart from a dopant.
13. The optoelectronic semiconductor chip according to claim 4 , wherein the optoelectronic semiconductor chip is a light-emitting diode emitting in the infrared range of the spectrum.