Power converter configured for limiting switching overvoltage
The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a bottom commutation cell that includes a bottom power electronic switch and a bottom compensation circuit connected to a bottom parasitic inductance. The bottom compensation circuit applies a sample of the voltage induced across the bottom parasitic inductance at turn-off of the bottom power electronic switch to the reference node of the bottom gate driver. The power converter also comprises a top commutation cell that includes top power electronic switch and a top compensation circuit connected to the bottom parasitic inductance. The top compensation circuit applies a sample of the voltage induced across the bottom parasitic emitter upon turn-off of the top power electronic switch to the reference node of the top gate driver. The top and bottom commutation cells are part of a loop, being connected at a junction of the collector of the bottom power electronic switch and the emitter of the top power electronic switch.
1. A power converter configured for limiting switching overvoltage, comprising:
a bottom commutation cell including a bottom power electronic switch having a bottom gate, a bottom gate driver and a bottom compensation circuit connected to a bottom parasitic inductance to apply a sample of a voltage induced across the bottom parasitic inductance to the bottom gate driver at turn-off of the bottom power electronic switch; and
a top commutation cell including a top power electronic switch having a top gate, a top gate driver and a top compensation circuit connected to the bottom parasitic inductance to apply a sample of a voltage induced across the bottom parasitic inductance to the top gate driver at turn-off of the top power electronic switch;
wherein the top and bottom commutation cells are part of a loop, being connected at a junction of a collector of the bottom power electronic switch and of an emitter of the top power electronic switch;
wherein the top compensation circuit comprises a turn-off diode configured to place a top resistive gain adapter having fourth resistor and in series with a fifth resistors when turning-off the top power electronics switch, the fourth and fifth resistor forming a top resistive gain adapter which defines a third voltage gain of the top compensation circuit, the third voltage gain being applied in sampling the voltage induced across the bottom parasitic inductance upon turn-off of the top power electronic switch, the top compensation circuit further comprising a top turn-on diode configured to place a sixth resistor in series with the fourth resistor when turning-on the top power electronic switch, the sixth and fourth resistors defining a fourth voltage gain of the top compensation circuit, the fourth voltage gain being applied in sampling the voltage induced across the top parasitic inductance at turn-on of the top power electronic switch.
2. The power converter of claim 1 , wherein the bottom parasitic inductance includes a parasitic emitter inductance of the bottom power electronic switch.
3. The power converter of claim 1 , wherein the bottom parasitic inductance includes a parasitic emitter inductance of the bottom power electronic switch and a parasitic negative voltage tab inductance.
4. The power converter of claim 1 , wherein applying the sample of the voltage induced across the bottom parasitic inductance at turn-off of the bottom power electronic switch controls the voltage induced across the bottom parasitic inductance.
5. The power converter of claim 1 , wherein the bottom gate driver has a bottom reference to receive the sample of the voltage induced across the bottom parasitic inductance from the bottom compensation circuit and the top gate driver has a top reference to receive the sample of the voltage induced across the bottom parasitic inductance from the top compensation circuit.
6. The power converter of claim 1 , wherein:
the bottom compensation circuit is configured to apply the sample of the voltage induced across the bottom parasitic inductance to the bottom gate driver at turn-off of the bottom power electronic switch using a first voltage gain; and
the bottom compensation circuit is configured to apply another sample of the voltage induced across the bottom parasitic inductance to the bottom gate driver at turn-on of the bottom power electronic switch using a second voltage gain lower than the first voltage gain and greater than or equal to zero.
7. The power converter of claim 6 , wherein the bottom compensation circuit comprises a bottom resistive gain adapter having first and second resistors defining the first voltage gain and a bottom turn-on diode configured to place a third resistor in parallel with the first resistor when turning-on the bottom power electronic switch, the first, second and third resistors defining the second voltage gain.
8. The power converter of claim 1 , comprising a bottom freewheel diode in parallel with the bottom power electronic switch, wherein the turn-off diode is selected such that a voltage drop across the turn-off diode is greater than a voltage drop across the bottom freewheel diode.
9. The power converter of claim 8 , wherein the turn-off diode comprises two turn-off diodes connected in series.
10. The power converter of claim 1 , wherein the top compensation circuit is configured to apply a sample of a voltage induced across a top parasitic inductance at turn-on of the top power electronic switch.
11. The power converter of claim 10 , wherein the top parasitic inductance is a parasitic emitter inductance of the top power electronic switch.
12. The power converter of claim 10 , wherein the top parasitic inductance includes a parasitic emitter inductance of the top power electronic switch and a parasitic collector inductance of the bottom power electronic switch.
13. The power converter of claim 1 , comprising an input capacitance, wherein the input capacitance closes the loop formed with the top and bottom commutation cells.