IP Library › Granted Patent US 10,649,787
Granted Patent B2
US 10,649,787 · App. 15/759,907 · Granted May 12, 2020

Exception handling involving emulation of exception triggering data transfer operation using syndrome data store that includes data value to be transferred

Inventors: Jason Parker (Sheffield, GB); Richard Roy Grisenthwaite (Cambridge, GB)
Assignee: ARM Limited
G06F9/3865G06F9/30043G06F9/30098G06F9/3861G06F9/45533
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Quick Facts
Patent No.
US 10,649,787
App. No.
15/759,907
Granted
May 12, 2020
Kind
B2
Abstract

A data processing system includes exception handling circuitry to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank. Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

Claims (48)

1. Apparatus for processing data comprising:

a plurality of registers;

exception handling circuitry to detect attempted execution of an exception-triggering processing operation including a transfer of a data value with a given register of said plurality of registers and to trigger execution of exception handling program instructions to at least partially emulate said exception-triggering processing operation; and

a syndrome data store to store syndrome data characterising said exception-triggering processing operation and including said data value; wherein

said exception handling circuitry performs said transfer with said given register using said data value within said syndrome data;

said syndrome data comprises replay state data having a first state and a second state;

when said replay state data has said second state and upon attempted execution of said exception-triggering processing operation, said exception handling circuitry sets said replay state data to said first state, and triggers execution of said exception handling program instructions;

when said replay state data has said first state and upon attempted execution of said exception-triggering processing operation, said exception handling circuitry sets said replay state data to said second state, suppresses triggering of said exception handling program instructions and signals said exception-triggering processing operation as complete.

2. Apparatus as claimed in claim 1 , wherein

said exception-triggering processing operation is a load operation to transfer said data value from a memory address to said given register;

said exception handling program instructions transfer said data value from said memory address to said syndrome data store; and

said exception handling circuitry transfers said data value from said syndrome data store to said given register upon attempted re-execution of said load operation.

3. Apparatus as claimed in claim 1 , wherein

said exception-triggering processing operation is a store operation to transfer said data value from said given register to a memory address;

said exception handling circuitry transfers said data value from said given register to said syndrome data store upon said attempted execution of said load operation; and

said exception handling program instructions transfer said data value from said syndrome data store to said memory address.

4. Apparatus as claimed in claim 1 , wherein when said replay state data has said first state and upon attempted execution of said exception-triggering processing operation, said exception handling circuitry transfers said data value from said syndrome data store to said given register.

5. Apparatus as claimed in claim 1 , wherein upon completion of said exception handling program instructions, said exception handling circuitry triggers attempted re-execution of said exception triggering processing operation.

6. Apparatus as claimed in claim 1 , wherein said syndrome data is part of current program status data saved and restored upon exception entry and exit.

7. Apparatus as claimed in claim 1 , wherein said exception-triggering processing operation triggers a data abort.

8. Apparatus as claimed in claim 1 , wherein a program instruction corresponding to said exception-triggering processing operation is part of a guest program and said exception handling program instructions are part of a virtualisation program providing an execution environment for said guest program.

9. Apparatus as claimed in claim 8 , comprising a memory management unit to manage access to a memory in dependence upon mapping data including first stage mapping data and second stage mapping data, wherein said guest program manages said first stage mapping data, said virtualisation program manages said second stage mapping data, and said exception-triggering processing operation is detected using said second stage mapping data.

10. Apparatus as claimed in claim 8 , wherein said virtualisation program is blocked from access to private state data of said guest program.

11. Apparatus as claimed in claim 10 , wherein said private state data includes data values within said plurality of registers during execution of said guest program.

12. Apparatus as claimed in claim 10 , wherein said first stage mapping blocks access to said private state data of said guest program by said virtualisation program.

13. Apparatus as claimed in claim 1 , wherein said transfer is between said given register and an input/output device.

14. Apparatus as claimed in claim 1 , wherein said syndrome data comprises address data indicating a memory address, and said transfer of said data value is between said given register and said memory address.

15. Apparatus as claimed in claim 1 , wherein said syndrome data comprises size data of said data value.

16. Apparatus as claimed in claim 1 , wherein said syndrome data specifies if said transfer is a load of said data value to said given register or a write of said data value from said given register.

17. Apparatus as claimed in claim 1 , wherein said syndrome data store is a syndrome register.

18. Apparatus for processing data comprising:

a plurality of register means for storing data;

exception handling means for detecting attempted execution of an exception-triggering processing operation including a transfer of a data value with a given register means of said plurality of register means and for triggering execution of exception handling program

instructions to at least partially emulate said exception-triggering processing operation; and

syndrome data storage means for storing syndrome data characterising said exception-triggering processing operation and including said data value; wherein

said exception handling means performs said transfer with said given register means using said data value within said syndrome data;

said syndrome data comprises replay state data having a first state and a second state;

when said replay state data has said second state and upon attempted execution of said exception-triggering processing operation, said exception handling means sets said replay state data to said first state, and triggers execution of said exception handling program instructions; and

when said replay state data has said first state and upon attempted execution of said exception-triggering processing operation, said exception handling means sets said replay state data to said second state, suppresses triggering of said exception handling program instructions and signals said exception-triggering processing operation as complete.

19. A method of processing data comprising:

storing data within a plurality of registers;

detecting attempted execution of an exception-triggering processing operation including a transfer of a data value with a given register of said plurality of registers;

triggering execution of exception handling program instructions to at least partially emulate said exception-triggering processing operation; and

storing syndrome data characterising said exception-triggering processing operation and including said data value; and

performing said transfer with said given register using said data value within said syndrome data;

said syndrome data comprises replay state data having a first state and a second state;

when said replay state data has said second state and upon attempted execution of said exception-triggering processing operation, said detecting attempted execution sets said replay state data to said first state, and triggers execution of said exception handling program instructions; and

when said replay state data has said first state and upon attempted execution of said exception-triggering processing operation, said detecting attempted execution sets said replay state data to said second state, suppresses triggering of said exception handling program instructions and signals said exception-triggering processing operation as complete.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2018
From: PARKER, JASON; GRISENTHWAITE, RICHARD ROY
To: ARM LIMITED
Reel/Frame 045203/0198 →
Priority Claims (1)
GB 1518165.4 · Oct 14, 2015 · national
Continuity (1)
Related Publication 20180239607A1 · Aug 23, 2018