Display panel, manufacturing method thereof and display device

1. A display panel, comprising a thin film transistor, a micro light emitting diode configured above the thin film transistor and electrically coupled to the thin film transistor, wherein the micro light emitting diode comprises a P type semiconductor, a N type semiconductor oppositely configured to the P type semiconductor and a light emitting layer configured between the P type semiconductor and the N type semiconductor, and the N type semiconductor is configured at one side of the P type semiconductor away from the thin film transistor, a thickness of the N type semiconductor being larger than a thickness of the P type semiconductor, one side of the N type semiconductor away from the P type semiconductor being a rough surface,

wherein an organic layer is stacked on the thin film transistor and an open groove is configured in the organic layer, the micro light emitting diode being accepted in the open groove and electrically coupled to the thin film transistor; and a passivation layer is stacked on and covers the organic layer and the micro light emitting diode; and

wherein a first electrode is stacked on the thin film transistor and is configured in the open groove of the organic layer, the thin film transistor comprising a source and a drain, one end of the first electrode being coupled to the source and the drain, another end of the first electrode being electrically coupled to the P type semiconductor; and a second electrode is stacked on the passivation layer, one end of the second electrode being electrically coupled to the N type semiconductor by penetrating through the passivation layer to electrically connect with the rough surface of the N type semiconductor.

2. The display panel according to claim 1 , wherein the passivation layer is an organic insulating film layer or an inorganic insulating film layer.

3. The display panel according to claim 1 , wherein one surface of the P type semiconductor facing the first electrode is stacked with a transparent conductive layer, and the first electrode is electrically coupled to the P type semiconductor with the transparent conductive layer.

4. The display panel according to claim 1 , wherein one side of the N type semiconductor away from the P type semiconductor is configured with a N type metal electrode, and the second electrode is electrically coupled to the N type semiconductor with the N type metal electrode.

5. The display panel according to claim 1 , wherein the thickness of the N type semiconductor is larger than 2 μm and the thickness of the P type semiconductor is smaller than 200 nm.

6. A display device, comprising a display device main body and a display panel, in which the display panel is electrically coupled to the display device main body, wherein the display panel comprises a thin film transistor, a micro light emitting diode configured above the thin film transistor and electrically coupled to the thin film transistor, wherein the micro light emitting diode comprises a P type semiconductor, a N type semiconductor oppositely configured to the P type semiconductor and a light emitting layer configured between the P type semiconductor and the N type semiconductor, and the N type semiconductor is configured at one side of the P type semiconductor away from the thin film transistor, a thickness of the N type semiconductor being larger than a thickness of the P type semiconductor, one side of the N type semiconductor away from the P type semiconductor being a rough surface,

wherein an organic layer is stacked on the thin film transistor and an open groove is configured in the organic layer, the micro light emitting diode being accepted in the open groove and electrically coupled to the thin film transistor; and a passivation layer is stacked on and covers the organic layer and the micro light emitting diode; and

wherein a first electrode is stacked on the thin film transistor and is configured in the open groove of the organic layer, the thin film transistor comprising a source and a drain, one end of the first electrode being coupled to the source and the drain, another end of the first electrode being electrically coupled to the P type semiconductor; and a second electrode is stacked on the passivation layer, one end of the second electrode being electrically coupled to the N type semiconductor by penetrating through the passivation layer to electrically connect with the rough surface of the N type semiconductor.

7. The display device according to claim 6 , wherein the passivation layer is an organic insulating film layer or an inorganic insulating film layer.

8. The display device according to claim 6 , wherein one surface of the P type semiconductor facing the first electrode is stacked with a transparent conductive layer, and the first electrode is electrically coupled to the P type semiconductor with the transparent conductive layer.

9. The display device according to claim 6 , wherein one side of the N type semiconductor away from the P type semiconductor is configured with a N type metal electrode, and the second electrode is electrically coupled to the N type semiconductor with the N type metal electrode.

10. The display device according to claim 6 , wherein the thickness of the N type semiconductor is larger than 2 μm and the thickness of the P type semiconductor is smaller than 200 nm.