IP Library Granted Patent US 10,148,475
Granted Patent B1
US 10,148,475 · App. 15/775,314 · Granted Dec 4, 2018

Receiver to process a load modulated analog input signal

Inventor: Jakob Jongsma (Graz, AT)
Assignee: PANTHRONICS AG
H04L27/22
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Quick Facts
Patent No.
US 10,148,475
App. No.
15/775,314
Granted
Dec 4, 2018
Kind
B1
Abstract

A receiver receives a load modulated analog input signal and outputs digital data detected in the input signal. An in-phase correlator and a quadrature-phase correlator for each of an in-phase component and an quadrature-phase component correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal. A combiner combines four output signals of the two in-phase correlators and the two quadrature-phase correlators. A slicer samples an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal.

Claims (24)

1. A receiver that receives a load modulated analog input signal and outputs digital data detected in the input signal, comprising:

an in-phase mixer that mixes the input signal with an in-phase carrier frequency and provides an in-phase component of the down-converted input signal and a quadrature-phase mixer that mixes the input signal with a quadrature-phase carrier frequency and provides a quadrature-phase component of the down-converted input signal;

an amplifier to amplify the in-phase component and the quadrature-phase component of the down-converted input signal;

a direct current (DC) block filter to remove the DC component of the in-phase component and the quadrature-phase component;

an in-phase correlator and a quadrature-phase correlator for each of the in-phase component and the quadrature-phase component to correlate the in-phase component and the quadrature-component with an in-phase component and a quadrature-phase component of a subcarrier or code clock frequency of the input signal;

a combiner to combine four output signals of the two in-phase correlators and the two quadrature-phase correlators;

a slicer to sample an output signal of the combiner at maximum energy levels to output the digital data detected in the input signal.

2. The receiver according to claim 1 , wherein each of the in-phase correlators and quadrature-phase correlators comprises:

a mixer to mix the in-phase component and the quadrature-phase component from the DC block filter with the in-phase component quadrature-phase component of the subcarrier or code clock frequency;

an integrator to continuously integrate the in-phase component quadrature-phase component from mixer over time during an integration window.

3. The receiver according to claim 2 , wherein the duration of the integration window depends on a modulation type of the load modulated analog input signal and is fixed for the modulation types according to standard ISO14.443 or standard FeliCa as follows:

ISO14.443 Type A to four sub-carrier periods;

ISO14.443 Type B to eight sub-carrier periods for a data rate of 106 kbit/s;

ISO14.443 Type B to four sub-carrier periods for a data rate of 212 kbit/s;

ISO14.443 Type B to two sub-carrier periods for a data rate of 424 kbit/s;

ISO14.443 Type B to one sub-carrier periods for a data rate of 848 kbit/s;

FeliCa to one sub-carrier periods.

4. The receiver according to claim 1 , wherein the combiner is built to add the four output signals of the two in-phase correlators and the two quadrature-phase correlators to generate the output signal of the combiner.

5. The receiver according to claim 1 , wherein the combiner is built to select at least one and in particular two of the four output signals of the two in-phase correlators and the two quadrature-phase correlators with the strongest energy levels and to add these selected signals to generate the output signal of the combiner.

6. The receiver according to claim 5 , wherein the slicer is built to use the information from the combiner which of the four output signals of the two in-phase correlators and the two quadrature-phase correlators were selected to select an appropriately aligned bit-clock to sample the output signal of the combiner.

7. The receiver according to claim 1 , wherein the correlators correlate each of the in-phase component and the quadrature-phase component of the load modulated analog input signal with the in-phase component and the quadrature-phase component of the subcarrier or code clock frequency dependent on a modulation type of the load modulated analog input signal which is fixed for the modulation types according to standard ISO14.443 or standard FeliCa as follows:

ISO14.443 Type A and B with a square wave that represents the subcarrier frequency;

FeliCa with a square wave that represents the Manchester clock frequency.

8. The receiver according to claim 1 , further comprising a filter to filter unwanted mixing products from the in-phase component and the quadrature-phase component of the load modulated analog input signal.

Assignments (2)
CHANGE OF NAME Recorded Nov 20, 2023
From: PANTHRONICS AG
To: RENESAS DESIGN AUSTRIA GMBH
Reel/Frame 065629/0299 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2018
From: JONGSMA, JAKOB
To: PANTHRONICS AG
Reel/Frame 045773/0728 →
Priority Claims (1)
EP 15194659 · Nov 16, 2015 · regional
Cited By (2)
US 12,562,766 US 12,562,780