IP Library Granted Patent US 10,887,439
Granted Patent B2
US 10,887,439 · App. 15/777,093 · Granted Jan 5, 2021

Microelectronic devices designed with integrated antennas on a substrate

Inventors: Telesphor Kamgaing (Chandler, AZ); Georgios C. Dogiamis (Chandler, AZ); Vijay K. Nair (Mesa, AZ)
Assignee: Intel Corporation
H04M1/0277G06F1/1613G06F1/1698H01Q1/243H01Q1/38H01Q1/40H01Q1/405H01Q9/0414H01Q21/0093H01Q21/22H01Q21/28H01Q23/00H01Q25/00H01L2223/6677H01L2224/16227H01L2224/32245H01L2224/73253H01L2924/15311H01Q1/2283H01Q3/26
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,887,439
App. No.
15/777,093
Granted
Jan 5, 2021
Kind
B2
Abstract

Embodiments of the invention include a microelectronic device that includes a die having at least one transceiver unit, a redistribution package coupled to the die, and a substrate coupled to the redistribution package. The substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

Claims (39)

1. A microelectronic device comprising:

a die having at least one transceiver unit;

a redistribution package coupled to the die; and

a substrate coupled to the redistribution package, the substrate having microvias and an antenna unit for transmitting and receiving communications, and wherein the substrate has a lower circuit density than a circuit density of the redistribution package, and

wherein the antenna unit for the transmitting and receiving communications includes a phase array antenna.

2. The microelectronic device of claim 1 , wherein the redistribution package comprises one or two conductive layers for coupling signals from the die having a first routing pitch to the substrate having a second routing pitch.

3. The microelectronic device of claim 1 , wherein the substrate comprises a printed circuit board.

4. The microelectronic device of claim 3 , wherein the printed circuit board is designed without high density interconnect.

5. The microelectronic device of claim 1 , wherein the redistribution package further comprises:

at least one of overmolded passive components and an integrated passive die (IPD) that includes passives for passive matching networks, power delivery, digital and analog functions.

6. The microelectronic device of claim 1 , wherein the microelectronic device comprises a 5G package architecture for 5G communications.

7. A microelectronic device, comprising:

a first die having at least one transceiver unit;

a first redistribution package coupled to the first die; and

a substrate coupled to the first redistribution package, the substrate having microvias and an integrated antenna unit for transmitting and receiving communications and also having a first cavity with the first die and the first redistribution package being positioned within the first cavity, and wherein the substrate has a lower circuit density than a circuit density of the redistribution package, and

wherein the integrated antenna unit for the transmitting and receiving communications includes a bore sight radiating antenna and at least one side radiating antenna.

8. The microelectronic device of claim 7 , wherein the first redistribution package comprises one or two conductive layers for coupling signals from the first die having a first routing pitch to the substrate having a second routing pitch.

9. The microelectronic device of claim 7 , wherein the substrate comprises a printed circuit board.

10. The microelectronic device of claim 9 , wherein the printed circuit board is designed without high density interconnect.

11. The microelectronic device of claim 7 , further comprising:

a second die having at least one transceiver unit;

a second redistribution package coupled to the second die, wherein the second die and the second redistribution package are positioned within the first cavity upon assembly.

12. The microelectronic device of claim 7 , wherein the substrate further comprises at least one additional cavity with each additional cavity including at least one die and at least one redistribution package.

13. A computing device comprising:

at least one processor to process data; and

a communication module or chip coupled to the at least one processor, wherein the communication module or chip includes:

a first die having at least one transceiver unit:

a first redistribution package coupled to the first die; and

a substrate coupled to the first redistribution package, the substrate having microvias and an integrated antenna unit for transmitting and receiving communications and also having a first cavity with the first die and the first redistribution package are positioned within the first cavity, and wherein the substrate has a lower circuit density than a circuit density of the redistribution package, and

wherein the integrated antenna unit for the transmitting and receiving communications includes a bore sight radiating antenna and at least one side radiating antenna.

14. The computing device of claim 13 , wherein the first redistribution package comprises one or two conductive layers for coupling signals from the first die having a first routing pitch to the substrate having a second routing pitch.

15. The computing device of claim 14 , wherein the substrate comprises a printed circuit board.

16. The computing device of claim 15 , wherein the printed circuit board is designed without high density interconnect.

17. The computing device of claim 13 , further comprising:

a thermal interface material applied to a surface of the first die; and a first heat sink coupled to the first die to cool the first die.

18. The computing device of claim 13 , further comprising:

a second die having at least one transceiver unit;

a second heat sink coupled to the second die to cool the second die; and

a second redistribution package coupled to the second die, wherein the substrate further comprises a second cavity with the second die and the second redistribution package being positioned within the second cavity upon assembly.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: DOGIAMIS, GEORGIOS C.; KAMGAING, TELESPHOR; NAIR, VIJAY K.
To: INTEL CORPORATION
Reel/Frame 053765/0266 →
Continuity (1)
Related Publication 20180332151A1 · Nov 15, 2018
Cited By (2)
US 12,322,853 US 12,374,799