IP Library Granted Patent US 11,075,070
Granted Patent B2
US 11,075,070 · App. 15/777,859 · Granted Jul 27, 2021

Monocrystalline semiconductor wafer and method for producing a semiconductor wafer

Inventors: Klaus Roettger (Bachmehring, DE); Herbert Becker (Burghausen, DE); Leszek Mistur (Burghausen, DE); Andreas Muehe (Wetzlar, DE)
Assignee: SILTRONIC AG
H01L21/02013H01L21/02016H01L21/02019H01L21/02021H01L21/02024H01L21/02052H01L21/3046H01L21/30625H01L21/67051H01L22/12H01L22/20H01L29/16
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,075,070
App. No.
15/777,859
Granted
Jul 27, 2021
Kind
B2
Abstract

A monocrystalline semiconductor wafers have an average roughness R a of at most 0.8 nm at a limiting wavelength of 250 μm, and an ESFQR avg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.

Claims (22)

1. A monocrystalline semiconductor wafer having a front side, a back side, and an edge, and having, on the front side, an average roughness R a of at most 0.8 nm at a limiting wavelength of 250 μm, and an ESFQR avg of 8 nm or less given an edge exclusion of 1 mm.

2. The monocrystalline semiconductor wafer of claim 1 , wherein the ESFQR avg is 5 nm or less.

3. The monocrystalline semiconductor wafer of claim 2 , wherein the contents of copper and nickel, determined by means of poly-UTP are each at most 3×10 10 cm −2 .

4. The monocrystalline semiconductor wafer of claim 1 , wherein the contents of copper and nickel, determined by means of poly-UTP are each at most 3×10 10 cm −2 .

5. The monocrystalline semiconductor wafer of claim 1 , wherein the semiconductor wafer consists substantially of silicon.

6. The monocrystalline semiconductor wafer of claim 5 , which has a diameter of at least 300 mm.

7. The monocrystalline semiconductor wafer of claim 1 , wherein the average front side surface roughness Ra at a limiting wavelength of 250 μm is between 0.1 nm and 0.2 nm.

8. A method for producing a monocrystalline semiconductor wafer having a front side, a back side, and an edge, comprising the following steps in the indicated order:

a) simultaneous double-side polishing of the semiconductor wafer to produce polished front side and back side surfaces,

b) local material-removing processing of at least part of at least the front side surface of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to have material removed, in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and

c) polishing at least the front side surface of the semiconductor wafer,

wherein the front side has an average roughness Ra of at most 0.8 nm at a limiting wavelength of 250 μm, and an EFSQR avg of 8 nm or less given an edge exclusion of 1 mm.

9. The method of claim 8 , wherein the local material-removing processing is carried out after a location-dependent measurement of the geometry parameter measured after the simultaneous double-side polishing of the same semiconductor wafer.

10. The method of claim 9 , wherein the local material-removing processing is carried out on the basis of a known location-dependent measurement of the geometry parameter measured after an identical simultaneous double-side polishing of identical semiconductor wafers, without the semiconductor wafer that is to be treated itself being subjected to this measurement.

11. The method of claim 10 , wherein the geometry parameter is the parameter ESFQR.

12. The method of claim 9 , wherein the geometry parameter is the parameter ESFQR.

13. The method of claim 8 , wherein the geometry parameter is the parameter ESFQR.

14. The method of claim 8 , wherein the material-removing processing is carried out by means of a nozzle which is guided over the surface to be processed at a distance of 0.5 to 3 mm from the surface and through which the fluid jet comprising the suspended hard substance particles emerges, fluid accumulates between the nozzle and the surface, and wherein the material removal is predominantly achieved by fluid comprising suspended hard substance particles that flows out parallel to the surface between the surface and the edge of the nozzle.

15. The method of claim 8 , wherein not more than 1 μm of material is removed in the final polishing of the front side surface of the semiconductor wafer in step c).

16. The method of claim 8 , wherein during the simultaneous double-side polishing of the semiconductor wafer is produced with a profile having a defined elevation in a region in the vicinity of an edge of the wafer.

17. The method of claim 16 , wherein during the local material-removing processing the nozzle is guided in circular paths or spirally over the region in the vicinity of the edge in which the elevation is situated, such that the elevation is at least partly removed during the course of the local material-removing processing.

18. The method of claim 8 , wherein not more than 0.5 μm of material is removed in the final polishing of the front side surface of the semiconductor wafer in step c).

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2018
From: ROETTGER, KLAUS; BECKER, HERBERT; MISTUR, LESZEK; MUEHE, ANDREAS
To: SILTRONIC AG
Reel/Frame 045864/0435 →
Priority Claims (1)
DE 10 2015 224 933.6 · Dec 11, 2015 · national
Continuity (1)
Related Publication 20180342383A1 · Nov 29, 2018