Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm
Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
1. A method of an analog-to-digital converter, comprising:
generating a digital reference code;
converting the digital reference code to an analog reference voltage;
comparing an analog input voltage to the analog reference voltage to obtain a comparison output;
updating the digital reference code based on the comparison output; and
after repeating the converting, comparing, and updating up to a predetermined number of times, outputting the digital reference code as a digital output code representative of the analog input voltage,
wherein the predetermined number of times results in the digital output code representing the analog input voltage to at least:
a first bit accuracy when the analog input voltage falls within a first voltage range, and
a second bit accuracy different than the first bit accuracy when the analog input voltage falls within a second voltage range.
2. The method of claim 1 , wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least a third bit accuracy different than the first and second bit accuracies when the analog input voltage falls within a third voltage range.
3. The method of claim 1 , wherein:
the first bit accuracy corresponds to a 1-LSB (least significant bit) accuracy; and
the second bit accuracy corresponds to a 2-LSB accuracy.
4. The method of claim 1 , further comprising selecting a back-off process based on the comparing, wherein:
said updating comprises updating the digital reference code based on the selected back-off process.
5. The method of claim 1 , further comprising selecting, based on the comparing, a back-off process from a faster back-off process and a slower back-off process, wherein:
said updating comprises updating the digital reference code based on the selected back-off process.
6. The method of claim 1 , further comprising defining the first voltage range and the second voltage range such that the first voltage range has a higher probability than the second voltage range of including the analog input voltage.
7. The method of claim 1 , wherein said updating comprises updating the digital reference code based on a settling behavior of the comparison output.
8. A successive approximation analog-to-digital converter, comprising:
a digital-to-analog converter operable to convert a digital reference code to an analog reference voltage;
a comparator operable to compare an analog input voltage to the analog reference voltage generated by the digital-to-analog converter and generate a comparison output indicative of a comparison of the analog input voltage and the reference voltage; and
a search and decode logic module comprising one or more circuits operable to:
generate the digital reference code;
update the digital reference code based on the comparison output; and
after updating the digital reference code up to a predetermined number of times, output the digital reference code as a digital output code representative of the analog input voltage,
wherein the predetermined number of time results in the digital output code representing the analog input voltage to at least:
a first bit accuracy when the analog input voltage falls within a first voltage range, and
a second bit accuracy different than the first bit accuracy when the analog input voltage falls within a second voltage range.
9. The successive approximation analog-to-digital converter of claim 8 , wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least a third bit accuracy different than the first and second bit accuracies when the analog input voltage falls within a third voltage range.
10. The successive approximation analog-to-digital converter of claim 8 , wherein:
the first bit accuracy corresponds to a 1-LSB (least significant bit) accuracy; and
the second bit accuracy corresponds to a 2-LSB accuracy.
11. The successive approximation analog-to-digital converter of claim 8 , wherein the search and decode logic module is further configured to:
select a back-off process based on the comparison output; and
update the digital reference code based on the selected back-off process.
12. The successive approximation analog-to-digital converter of claim 8 , wherein the search and decode logic module is further configured to:
select, based on the comparison output, a back-off process from a faster back-off process and a slower back-off process; and
update the digital reference code based on the selected back-off process.
13. The successive approximation analog-to-digital converter of claim 8 , wherein the search and decode logic module is further configured to define the first voltage range and the second voltage range such that the first voltage range has a higher probability than the second voltage range of including the analog input voltage.
14. The successive approximation analog-to-digital converter of claim 8 , wherein the search and decode logic module is further configured to update the digital reference code based on a settling behavior of the comparator.
15. An apparatus, comprising:
a communication interface operable to receive analog signal; and
a successive approximation analog-to-digital converter operable to:
generate a digital reference code;
convert the digital reference code to an analog reference voltage;
compare an analog input voltage to the analog reference voltage to obtain a comparison output;
update the digital reference code based on the comparison output; and
after updating the digital reference code up to a predetermined number of times, outputting the digital reference code as a digital output code representative of the analog input voltage,
wherein the predetermined number of times results in the digital output code representing the analog input voltage to at least:
1-LSB (least significant bit) accuracy when the analog input voltage falls within a first voltage range, and
2-LSB accuracy when the analog input voltage falls within a second voltage range.
16. The apparatus of claim 15 wherein, wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least 4-LSB accuracy when the analog input voltage falls within a third voltage range.
17. The apparatus of claim 15 wherein, wherein the successive approximation analog-to-digital converter is further operable to:
select a back-off process based on the comparison output; and
update the digital reference code based on the selected back-off process.
18. The apparatus of claim 15 wherein, wherein the successive approximation analog-to-digital converter is further operable to:
select, based on the comparison output, a back-off process from a faster back-off process and a slower back-off process; and
update the digital reference code based on the selected back-off process.
19. The apparatus of claim 15 wherein, wherein the successive approximation analog-to-digital converter is further operable to define the first voltage range and the second voltage range such that the first voltage range has a higher probability than the second voltage range of including the analog input voltage.
20. The apparatus of claim 15 wherein, wherein the successive approximation analog-to-digital converter is further operable to update the digital reference code based on a settling behavior of the comparison output.