IP Library Granted Patent US 10,229,740
Granted Patent B2
US 10,229,740 · App. 15/783,780 · Granted Mar 12, 2019

Memory system of 3D NAND flash and operating method thereof

Inventors: Yu Cai (San Jose, CA); Haibo Li (Cupertino, CA); Fan Zhang (Fremont, CA); June Lee (Sunnyvale, CA)
Assignee: SK hynix Inc.
G11C16/10G11C16/0483G11C16/26G11C16/3427
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Quick Facts
Patent No.
US 10,229,740
App. No.
15/783,780
Granted
Mar 12, 2019
Kind
B2
Abstract

An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.

Claims (28)

1. An apparatus of a memory system comprising:

memory blocks, each of the memory blocks including strings, each of the stings having flash cells and select gates thereon, wherein

the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other,

in each of the memory blocks, the strings are arranged in groups, each of the groups including strings, at least one of the groups in each of the memory blocks including at least one string for a data read operation and at least one other string,

wherein, in a data read operation on a select one of the at least one of the groups in a select one of the memory blocks, the at least one string for the data read operation is on and the least one other string in the select group is off for boosting; and

wherein each of the groups has its own read counts management.

2. The apparatus recited in claim 1 wherein the at least one of the groups in each of the memory blocks is a data reading group, the rest of the groups being boosted groups, the at least one data reading group including the at least one of the groups that includes the at least one string that is on for the read operation and the boosted groups, including all strings therein, in the select memory block are off for boosting.

3. The apparatus recited in claim 2 wherein the boosted groups are selected for writing new data.

4. The apparatus recited in claim 1 wherein the flash cells are programmed along each of the strings, a subsequent string is programmed upon completion of programming a previous string.

5. The apparatus recited in claim 1 wherein the select gates include source-side select gates and drain-side select gates.

6. The apparatus recited in claim 5 wherein the flash cells are programmed across each of the strings within one of the groups, from the source-side select gates to the drain-side select gates.

7. The apparatus recited in claim 5 wherein the source-side select gates in each of the groups of each of the memory blocks share a same gate signal and a same source signal.

8. The apparatus recited in claim 1 wherein the read counts management of each of the groups includes recording the read counts of each of the groups.

9. The apparatus recited in claim 1 wherein the read counts management of each of the groups includes relocating data of a group when read counts thereof is greater than a threshold.

10. A method of operating a memory system comprising:

arranging memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon;

connecting the select gates of each of the strings with a same index number in each of the memory blocks with each other;

in each of the memory blocks, arranging the strings into groups, each of the groups including strings, at least one of the groups in each of the memory blocks including at least one string for a data read operation and at least one other string;

programming the flash cells including performing a data read operation on a select one of the at least one of the groups in a select one of the memory blocks, wherein the at least one string for the data read operation in the select group is on and the at least one other string in the select group is off for boosting; and

performing read counts management for each of the groups.

11. The method recited in claim 10 wherein the arranging the strings into groups includes forming at least one data reading group, and the rest of the groups as boosted groups, the at least one data reading group including the at least one of the groups that includes the at least one string that is on for the read operation and the boosted groups including all strings therein, in the select memory block are off for boosting.

12. The method recited in claim 11 wherein the boosted groups are selected for writing new data.

13. The method recited in claim 10 wherein the programming the flash cells includes programming the flash cells along each of the strings, programming a subsequent string is upon completion of programming a previous string.

14. The method recited in claim 10 wherein the arranging the memory blocks having select gates includes arranging the memory blocks having source-side select gates and drain-side select gates.

15. The method recited in claim 14 wherein the programming the flash cells includes programming the flash cells across each of the strings within one of the groups, from the source-side select gates to the drain-side select gates.

16. The method recited in claim 14 wherein the arranging the memory blocks having select gates includes arranging the memory blocks having source-side select gates in each of the groups of each of the memory blocks sharing a same gate signal and a same source signal.

17. The method recited in claim 10 wherein the performing read counts management of each of the groups includes recording the read counts of each of the groups.

18. The apparatus recited in claim 10 wherein the performing read counts management of each of the groups includes relocating data of a group when read counts thereof is greater than a threshold.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2017
From: CAI, YU; LI, HAIBO; ZHANG, FAN
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 044054/0065 →
Continuity (2)
Provisional Application 62409222 · Oct 17, 2016
Related Publication 20180108417A1 · Apr 19, 2018
Cited By (8)
US 12,530,287 US 12,530,288 US 12,573,469 US 12,597,472 US 12,609,161 US 12,640,207 US 12,645,582 US 12,711,061