Methods and apparatuses for requesting ready status information from a memory
Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.
1. An apparatus, comprising:
a memory; and
a host coupled to the memory and configured to provide a plurality of memory access requests to the memory, wherein the host is further configured to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, wherein the ready status information includes an estimated relative wait time before the memory may be ready to execute the memory access request, wherein the host is further configured to request execution of the memory access request after the estimated relative wait time has expired in response to only one of the plurality of memory access requests remaining queued for execution.
2. The apparatus of claim 1 , wherein the host is configured to request updated ready status information after the estimated relative wait time has elapsed.
3. The apparatus of claim 2 , wherein the host is further configured to request execution of the memory access request responsive to the updated ready status information.
4. The apparatus of claim 2 , wherein the host configured to request the updated ready status information after the estimated relative wait time has elapsed is in response to more than one of the plurality of memory access requests remaining queued for execution.
5. The apparatus of claim 1 , wherein the host is further configured to request execution of the plurality of memory access requests.
6. The apparatus of claim 1 , wherein the host is coupled to the memory via a command bus, wherein the host is configured to provide the request for ready status information to the memory via the command bus.
7. The apparatus of claim 6 , wherein the host is configured to receive the ready status information via the command bus.
8. The apparatus of claim 1 , wherein the ready status information is an indication as to whether the memory is ready to execute the plurality of memory access requests.
9. An apparatus, comprising:
a host configured to provide a plurality of memory access requests and a status request to a memory, wherein the host is further configured to receive ready status information from the memory, wherein the ready status information comprises an estimated relative wait time before the memory may be ready to execute a memory access request of the plurality of memory access requests, wherein the host is further configured to provide an execution request in response to expiration of the estimated relative wait time received via the ready status information, wherein the host configured to request updated ready status information after the estimated relative wait time has elapsed in response to more than one of the plurality of memory access requests remaining queued for execution.
10. The apparatus of claim 9 , wherein the ready status information is responsive to the status request.
11. The apparatus of claim 9 , wherein the ready status information is an indication as to whether the memory is ready to execute the plurality of memory access requests.
12. The apparatus of claim 9 , further comprising the memory comprising registers configured to store the indication of whether the memory is ready to execute the plurality of memory access requests and the indication of when the memory may be ready to execute the plurality of memory access requests.
13. The apparatus of claim 9 , wherein the host is further configured to wait to provide the execution request until the ready status information indicates that the plurality of memory access requests are ready for execution.
14. The apparatus of claim 13 , wherein the host comprises a queue status register configured to maintain respective indications of when the memory may be ready to execute each of the plurality of memory access requests.
15. The apparatus of claim 9 , wherein an order of when the plurality of memory access requests become ready for execution is based on respective priorities assigned by the host to the plurality of memory access requests.
16. A method, comprising:
providing a plurality of memory access requests to a memory;
requesting ready status information from the memory regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, wherein the ready status information includes an estimated relative wait time before the memory may be ready to execute the memory access request; and
requesting execution of the memory access request by the memory after the estimated relative wait time has expired in response to only one of the plurality of memory access requests remaining queued for execution.
17. The apparatus of claim 16 , further comprising requesting updated ready status information after the estimated relative wait time has elapsed.
18. The apparatus of claim 17 , further comprising requesting execution of the memory access request responsive to the updated ready status information.
19. The apparatus of claim 17 , wherein requesting the updated ready status information after the estimated wait time has elapsed is in response to more than one of the plurality of memory access requests remaining queued for execution.