Current limiting systems and methods

1. An integrated semi-conductor chip comprising:

an input component operable to receive a signal;

an integrated adjustable component coupled to the input component, the adjustable component configurable to operate:

in a first mode which includes a low resistance; and

in a second mode including a current limiting operation in which the second mode enables continued operation in a condition that is unsafe for operation in the first mode, wherein the condition includes potential thermal runaway in the first mode; and

an output component coupled to the adjustable component, the output component operable to forward a signal.

2. The integrated semi-conductor chip of claim 1 wherein the adjustable component is configurable to turn off when the condition becomes unsafe to operate in both the first mode and the second mode.

3. The integrated semi-conductor chip of claim 1 wherein a relatively large component configuration is activated in the first mode.

4. The integrated semi-conductor chip of claim 1 wherein a relatively small component configuration is activated in the second mode.

5. The integrated semi-conductor chip of claim 1 in which the first mode includes a relatively low drain to source on resistance compared to the second mode.

6. The integrated semi-conductor chip of claim 1 in which the second mode includes a relatively small component configuration that has an increased gate to source voltage compared to an attempt utilizing a relatively large component configuration in the first mode.

7. The integrated semi-conductor chip of claim 1 further comprising an integrated control component, wherein the integrated control component includes:

an amplifier coupled to the input component;

a first resistor and a second resistor coupled to the amplifier;

a current source coupled to the first resistor;

a control transistor coupled to the amplifier;

a sense transistor coupled to the amplifier; and

a switch coupled to the amplifier.

8. The integrated semi-conductor chip of claim 7 wherein the sense transistor, the small transistor component, the large transistor component share drain connections with the gates of the sense transitor and small transistor coupled to one another.

9. The integrated semi-conductor chip of claim 7 wherein the amplifier is an error amp of a control loop.

10. The integrated semi-conductor chip of claim 7 wherein the switch is closed during normal operation and the switch connects a gate of the large transitor component to gates of the sense transistor and the small transisor component.

11. The integrated semi-conductor chip of claim 7 wherein if an over-current condition is detected the switch opens disconnecting the large transistor component from the small transistor component and the sense transistor while the control transistor turns on and shorts the gate of large transitor component to the input component; and gates of the small transisor component and the sense transistor are regulated to support a designated current limit level.

12. An integrated circuit protection process comprising:

performing a current monitoring process; and

performing an internal configuration process of an integrated circuit comprising an integrated first transistor and an integrated second transistor, in which one configuration enables continued operation of the integrated system in conditions that are unsafe for operation in another configuration, wherein the condition includes potential thermal runaway in the other configuration, wherein a selection of a configuration is based upon results of the current monitoring.

13. The integrated circuit protection process of claim 12 wherein the configuration process comprises:

configuring components of a device to operate in a normal mode in which a relatively large component configuration is activated or implemented;

configuring components of a device to operate in a current protection mode in which a relatively small component configuration is activated or implemented; and

configuring components of a device for operation in a third mode which includes reducing current to at least some of the components of the device.

14. The integrated circuit protection process of claim 13 wherein the large component configuration is implemented with a relatively low drain to source on resistance when in the on state (Rds-on) as compared to the second mode.

15. The integrated circuit protection process of claim 13 wherein the relatively small component configuration includes a relatively increased gate to source voltage as compared utilizing the relatively large component configuration in the current protection mode.

16. The integrated circuit protection process of claim 15 wherein the increased gate source voltage moves operation of the relatively small component configuration into a region of characteristics with reduced propensity for thermal run away.

17. An integrated device comprising:

an integrated adjustable component selectively operable in a normal mode configuration and a current limiting mode configuration, in which the normal mode configuration includes a low resistance characteristic and the current limiting mode configuration includes detrimental current protection and thermal run-away avoidance within the integrated device, the current limiting mode configuration enables continued operation in conditions that are unsafe for operation in the normal mode configuration; and

an integrated control component configured to control a change in the adjustable component between the normal mode configuration and the current limiting mode configuration.

18. The integrated device of claim 17 wherein a relatively small component configuration is activated in current limiting mode configuration compared to the normal mode configuration.

19. The integrated device of claim 17 wherein the integrated control component includes a control loop and a sensing component and the integrated control component is configured to detect an adverse current condition and direct a configuration change in the integrated adjustable component to protect against the adverse current condition.

20. The integrated device of claim 17 wherein at least some configurations of the adjustable component configurations include an interdigitated design.