Semiconductor package

1. A semiconductor package comprising:

a substrate;

a semiconductor memory chip on the substrate;

a second semiconductor chip on the substrate and spaced laterally apart from the semiconductor memory chip;

a mold layer on the substrate and covering sides of the semiconductor memory chip and the second semiconductor chip; and

an image sensor unit on the semiconductor memory chip, the second semiconductor chip and the mold layer, the image sensor unit comprising:

a third semiconductor chip having integrated circuitry constituting a logic circuit electrically connected to the semiconductor memory chip, and

a fourth semiconductor chip stacked on the third semiconductor chip and comprising photodiodes that convert light into electric charges,

wherein the fourth semiconductor chip is electrically connected to the third semiconductor chip and the integrated circuit of the third semiconductor chip is configured to convert the electric charges generated by the photodiodes of the fourth semiconductor chip into an electrical signal, and

wherein the semiconductor package further comprises a connection pad on an upper surface of the image sensor unit, and a bonding wire electrically connecting the connection pad to a terminal of the substrate.

2. The semiconductor package according to claim 1 , wherein the second semiconductor chip is a dummy chip consisting of a single layer of silicon or metal.

3. The semiconductor package according to claim 1 , wherein the second semiconductor chip is a memory chip, a logic chip, a chip capacitor or a chip including a combination of at least two components selected from a group consisting of a memory, a logic circuit and a capacitor, and

the second semiconductor chip is electrically connected to the third semiconductor chip of the image sensor unit.

4. The semiconductor package according to claim 1 , wherein sides of the mold layer are substantially coplanar with sides of the third semiconductor chip and the fourth semiconductor chip of the image sensor unit.

5. The semiconductor package according to claim 1 , wherein the image sensor unit overlaps the semiconductor memory chip and the second semiconductor chip, in a plan view of the semiconductor package.

6. The semiconductor package according to claim 1 , further comprising a redistribution layer interposed between the mold layer and the image sensor unit, the redistribution layer electrically connected to the third semiconductor chip of the image sensor unit.

7. The semiconductor package according to claim 6 , wherein the semiconductor memory chip has an active surface facing toward the image sensor unit and electrically connected to the redistribution layer.

8. A semiconductor package comprising:

an image sensor unit having opposite major first and second surfaces, the image sensor unit including pixel regions at the major second surface thereof and photodiodes operatively associated with the pixel regions to sense light incident on the pixel regions;

a first lower semiconductor chip and a second lower semiconductor chip on the major first surface of the image sensor unit;

a mold layer on the major first surface of the image sensor unit and covering sides of the first and second lower semiconductor chips; and

a connection terminal interposed between the major first surface of the image sensor unit and the first lower semiconductor chip, the connection terminal electrically connecting the first lower semiconductor chip to the image sensor unit,

wherein the first lower semiconductor chip comprises a memory,

the image sensor unit comprises an upper semiconductor chip disposed over the first and second lower semiconductor chips and a sensing chip stacked on the upper semiconductor chip,

the upper semiconductor chip includes an integrated circuit constituting a logic circuit electrically connected to the photodiodes and to the memory,

the sensing chip comprises photodiodes, and

a sum of widths of the first and second lower semiconductor chips is smaller than a width of each of the upper semiconductor chip and the sensing chip of the image sensor unit, the widths being dimensions taken in a direction parallel to the major first and second surfaces of the image sensor unit, and

wherein the semiconductor package further comprises a connection pad on the major second surface of the image sensor unit, a substrate on lower surfaces of the first and second lower semiconductor chips opposite to upper surfaces thereof facing the major first surface of the image sensor unit, and a bonding wire electrically connecting the connection pad to a terminal of the substrate.

9. The semiconductor package according to claim 8 , wherein the first lower semiconductor chip is a memory chip, and

the second lower semiconductor chip is a dummy chip consisting of a single layer of silicon or metal.

10. The semiconductor package according to claim 8 , wherein the first lower semiconductor chip is a memory chip,

the second lower semiconductor chip includes a memory chip, a logic chip, a capacitor or a chip including a combination of at least two components selected from a group consisting of a memory, a logic circuit and a capacitor, and

the second lower semiconductor chip is electrically connected to the upper semiconductor chip of the image sensor unit.

11. The semiconductor package according to claim 8 , wherein the upper semiconductor chip comprises a via electrically connected to the integrated circuit, and

the via is connected to the connection terminal.

12. The semiconductor package according to claim 8 , wherein sides of the mold layer are substantially coplanar with sides of the upper semiconductor chip and the sensing chip of the image sensor unit.