Stress tuned stiffeners for micro electronics package warpage control
View Patent ↗A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.
1. A method of forming a semiconductor device assembly, the method comprising:
determining a first warpage of a first semiconductor device assembly comprised of a semiconductor device, a substrate, and a mold compound;
tuning a stiffener member based on the first warpage in order to form a second semiconductor device assembly having a second warpage, the second semiconductor device assembly comprised of the semiconductor device, the substrate, the mold compound, and the stiffener member;
forming the second semiconductor device assembly comprised of the semiconductor device positioned on the substrate, the mold compound encapsulating at least the semiconductor device, and the stiffener member;
wherein tuning the stiffener member further comprises configuring the stiffener member to have a desired coefficient of thermal expansion; and
wherein tuning the stiffener member further comprises varying a density of the stiffener member to obtain the desired coefficient of thermal expansion.
2. The method of claim 1 , wherein the second warpage substantially corresponds to a third warpage of a second semiconductor device or a third semiconductor device assembly.
3. The method of claim 1 , wherein turning the stiffener member further comprises positioning a plurality of stiffener members within the second semiconductor device assembly to obtain the second warpage.
4. The method of claim 3 , wherein positioning the plurality of stiffener members further comprises positioning the stiffener members in a predetermined pattern within the second semiconductor device assembly.
5. The method of claim 1 , wherein the stiffener member is a layer of controlled stress within the substrate or the semiconductor device.
6. The method of claim 1 , wherein tuning the stiffener member further comprises adding the stiffener member as a layer in situ in the substrate or the semiconductor device.