Vertical field effect transistor having U-shaped top spacer
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.
1. A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a substrate;
forming a high-k metal gate (HKMG) over the plurality of fins;
etching the HKMG to form recesses between the plurality of fins;
depositing a barrier layer within the recesses; and
etching the barrier layer and a hardmask formed over the plurality of fins to define substantially U-shaped spacers adjacent top portions of the plurality of fins.
2. The method of claim 1 , wherein an epitaxial layer is formed on the plurality of fins.
3. The method of claim 2 , wherein a nitride cap is deposited over the epitaxial layer.
4. The method of claim 3 , wherein air gaps are defined between the U-shaped spacers and the epitaxial layer.
5. The method of claim 1 , wherein the barrier layer is a silicon nitride (SiN) liner.
6. The method of claim 1 , wherein the U-shaped spacers contact at least one portion of their corresponding HKMG.
7. The method of claim 1 , wherein the U-shaped spacers are in alignment with at least one portion of their corresponding HKMG.
8. The method of claim 1 , wherein the U-shaped spacers have different sizes across the semiconductor structure.
9. A method of forming a semiconductor structure, the method comprising:
forming a plurality of fins over a substrate;
forming a plurality of conducting layers over the plurality of fins;
etching the plurality of conducting layers to form recesses between the plurality of fins;
depositing a barrier layer within the recesses; and
etching the barrier layer to define spacers over etched sections of the plurality of conducting layers.
10. The method of claim 9 , wherein the spacers are substantially U-shaped spacers.
11. The method of claim 10 , wherein an epitaxial layer is formed on the plurality of fins.
12. The method of claim 11 , wherein air gaps are defined between the U-shaped spacers and the epitaxial layer.
13. The method of claim 9 , wherein the plurality of conducting layers include a high-k dielectric layer, a work function material layer, and a tungsten (W) layer.
14. A semiconductor structure, comprising:
a plurality of fins formed over a substrate;
a high-k metal gate (HKMG) formed over the plurality of fins;
recesses formed between the plurality of fins by etching the HKMG;
a barrier layer deposited within the recesses; and
U-shaped spacers defined adjacent top portions of the plurality of fins by etching the barrier layer and a hardmask formed over the plurality of fins.
15. The structure of claim 14 , wherein an epitaxial layer is formed on the plurality of fins.
16. The structure of claim 15 , wherein a nitride cap is deposited over the epitaxial layer.
17. The structure of claim 16 , wherein air gaps are defined between the U-shaped spacers and the epitaxial layer.
18. The structure of claim 14 , wherein the barrier layer is a silicon nitride (SiN) liner.
19. The structure of claim 14 , wherein the U-shaped spacers contact at least one portion of their corresponding HKMG.
20. The structure of claim 14 , wherein the U-shaped spacers are in alignment with at least one portion of their corresponding HKMG.