Synchronous rectifier turn-on enable
A circuit includes a drain detect circuit. The drain detect circuit receives a sense signal from a secondary side of a power converter circuit, determines, using voltage values of the sense signal, whether a primary side switch of the power converter circuit has been turned on, and assert a switch on detect signal in response to determining that the primary side switch has been turned on. The circuit may assert an enable signal in response to the assertion of the switch on detect signal, and de-asserts the enable signal in response to an assertion of a control signal. The control signal may only allowed to be asserted when the enable signal is asserted. The control signal may control a Synchronous Rectifier device. The power converter circuit may be a flyback converter, and the primary side switch may control a current into a primary-side coil of a transformer.
1. A circuit comprising:
a drain detect circuit including a first comparator circuit, the drain detect circuit to:
receive a sense signal from a secondary side of a power converter circuit;
determine, using the first comparator circuit and a voltage value of the sense signal, whether a switch of the primary side of the power converter circuit has been turned on; and
assert a switch on detect signal in response to determining that the switch of the primary side has been turned on,
wherein the circuit asserts an enable signal in response to an assertion of the switch on detect signal,
wherein the circuit de-asserts the enable signal in response to an assertion of a control signal, and
wherein the enable signal controls whether the control signal is asserted.
2. The circuit of claim 1 , wherein the first comparator circuit is to determine that the switch of the primary side has been turned on in response to the voltage value of the sense signal being greater than a first predetermined detect value.
3. The circuit of claim 2 , wherein a magnitude of the first predetermined detect value is greater than a magnitude of an output voltage of the power converter circuit.
4. The circuit of claim 2 , wherein the drain detect circuit further comprises:
a pulse detect circuit to determine that the switch of the primary side has been turned on when the voltage value of the sense signal is greater than a second predetermined detect value for longer than a predetermined duration.
5. The circuit of claim 4 , wherein the pulse detect circuit comprises:
a second comparator circuit to generate a detect signal according to whether the voltage value of the sense signal is greater than the second predetermined detect value; and
a pulse width comparator circuit to determine that the switch of the primary side has been turned on when the detect signal is asserted for longer than a predetermined duration.
6. The circuit of claim 4 , wherein a magnitude of the second predetermined detect value is less than the magnitude of output voltage of the power converter circuit.
7. The circuit of claim 4 , wherein the predetermined duration is determined according to a predetermined duration voltage value.
8. The circuit of claim 1 , wherein the drain detect circuit comprises:
a pulse detect circuit to determine that the switch of the primary side has been turned on when the voltage value of the sense signal is greater than a predetermined detect value for longer than a predetermined duration.
9. The circuit of claim 1 , further comprising:
a drain sense circuit to:
receive the sense signal,
determine, using a voltage value of the sense signal and a predetermined on threshold value, an on signal,
determine, using a voltage value of the sense signal and a predetermined off threshold value, an off signal;
wherein the circuit asserts the control signal in response to the on signal being asserted and the enable signal being asserted; and
wherein the circuit de-asserts the control signal in response to the off signal being asserted.
10. The circuit of claim 9 ,
wherein determining whether a switch of the primary side of the power converter circuit has been turned on includes comparing the voltage value of the sense signal to a predetermined detect value; and
wherein a polarity of the predetermined detect value is opposite a polarity of the predetermined on threshold.
11. A circuit comprising:
a drain detect circuit that receives a sense signal and determines a QDET signal using to the sense signal and one or more of a predetermined high detect threshold and a predetermined middle detect threshold;
a first flip flop circuit that asserts an enable signal in response to an assertion of the QDET signal and de-asserts the enable signal in response to the assertion of a control signal;
an AND gate that receives the enable signal on a first input and receives an on signal on a second input;
a second flip flop circuit that asserts the control signal in response to the assertion of the output of the AND gate and de-asserts the control signal in response to the assertion of an off signal.
12. The circuit of claim 11 , further comprising:
a drain sense circuit that receives the sense signal, determines the on signal according to the sense signal and a predetermined on threshold, and determines the off signal according to the sense signal and a predetermined on threshold.
13. The circuit of claim 11 , wherein the drain detect circuit comprises:
a comparator to generate a detect output by comparing the sense signal to the predetermined high detect threshold;
wherein drain detect circuit produces the QDET signal using the detect output.
14. The circuit of claim 11 , wherein the drain detect circuit comprises:
a comparator to generate a TDRAIN signal by comparing the sense signal to the predetermined middle detect threshold; and
a pulse width comparator circuit to produce a detect output according to whether a pulse of the TDRAIN signal has a duration greater than a predetermined duration,
wherein drain detect circuit produces the QDET signal using the detect output.
15. A method for controlling a Synchronous Rectifier (SR) device, the method comprising:
receiving a sense signal from a conduction terminal of an SR device, the SR device being included in a secondary side of a power converter circuit; and
generating a control signal for a control terminal of the SR device, generating the control signal including:
disabling assertion of the control signal in response to the control signal being asserted;
determining, using the sense signal, whether a switching device has been turned on, the switching device being included in a primary side of the power converter circuit; and
enabling assertion of the control signal in response to determining that the switching device included in the primary side has been turned on.
16. The method of claim 15 , wherein determining whether the switching device has been turned on includes determining that the switching device has been turned on in response to the sense signal having a voltage value higher than an predetermined high detect value.
17. The method of claim 15 , wherein determining whether the switching device has been turned on includes determining that the switching device has been turned on in response to the sense signal having a voltage value higher than an predetermined middle detect value for an uninterrupted interval greater than a predetermined interval.
18. The method of claim 17 , wherein determining whether the switching device has been turned on includes determining that the switching device has been turned on in response to the sense signal having a voltage value higher than an predetermined high detect value.
19. The method of claim 17 , wherein the predetermined duration is determined according to a period of a ringing of the conduction terminal and an expected minimum duration of the switching device being been turned on.