Current-controlled CMOS logic family
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C 3 MOS logic with low power conventional CMOS logic. The combined C 3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
1. An apparatus comprising:
an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
CMOS circuitry, within the integrated circuitry, configured to:
receive a plurality of signals; and
process the plurality of signals to generate another plurality of signals; and
CMOS circuitry, within the integrated circuitry, configured to:
receive the another plurality of signals from the CMOS circuitry; and
process the another plurality of signals to generate a signal.
2. The apparatus of claim 1 , wherein:
each of the plurality of signals has a first frequency; and
the signal is a serialized signal that is based on the plurality of signals and has a second frequency that is different than the first frequency.
3. The apparatus of claim 1 , wherein the integrated circuitry is configured to process data compliant with a fiber channel, and wherein at least one of the plurality of signals or the signal includes the data compliant with the fiber channel.
4. The apparatus of claim 1 , wherein the CMOS logic is further configured to operate as a flip-flop.
5. The apparatus of claim 1 further comprising:
wherein the C 3 MOS circuitry is coupled to a first power supply voltage;
wherein the CMOS circuitry is coupled to a second power supply voltage that is different than the first power supply voltage; and
connecting circuitry between the C 3 MOS circuitry and the CMOS circuitry, wherein one of: the connecting circuitry facilitates output of the CMOS circuitry being received as input to the C 3 MOS circuitry or the connecting circuitry facilitates output of the C 3 MOS circuitry being received as input to the CMOS circuitry.
6. The apparatus of claim 1 , wherein:
the C 3 MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein:
a current steering circuit within the C 3 MOS logic including the first source and the second source;
the first source and the second source being coupled together and to a current source;
the first drain and the second drain being coupled to a power supply; and
the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal.
7. An apparatus comprising:
an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
CMOS circuitry, within the integrated circuitry, configured to:
receive a signal; and
process the signal to generate a plurality of signals; and
CMOS circuitry, within the integrated circuitry, configured to:
receive the plurality of signals from the CMOS circuitry;
process the plurality of signals to generate another plurality of signals; and
output the plurality of signals.
8. The apparatus of claim 7 , wherein:
the signal is a serialized signal that has a first frequency; and
each of the plurality of signals has a second frequency that is different than the first frequency.
9. The apparatus of claim 7 , wherein the integrated circuitry is configured to process data compliant with a fiber channel, and wherein at least one of the signal or the plurality of signals includes the data compliant with the fiber channel.
10. The apparatus of claim 7 , wherein the C 3 MOS logic is further configured to operate as a flip-flop.
11. The apparatus of claim 7 further comprising:
wherein the C 3 MOS circuitry is coupled to a first power supply voltage;
wherein the CMOS circuitry is coupled to a second power supply voltage that is different than the first power supply voltage; and
connecting circuitry between the CMOS circuitry and the CMOS circuitry, wherein one of: the connecting circuitry facilitates output of the CMOS circuitry being received as input to the CMOS circuitry or the connecting circuitry facilitates output of the CMOS circuitry being received as input to the CMOS circuitry.
12. The apparatus of claim 7 , wherein:
the CMOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein:
a current steering circuit within the CMOS logic including the first source and the second source;
the first source and the second source being coupled together and to a current source;
the first drain and the second drain being coupled to a power supply; and
the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal.
13. An apparatus comprising:
an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (CMOS) logic;
CMOS circuitry, within the integrated circuitry, configured to:
receive a signal;
process the signal to generate a first plurality of signals;
first CMOS circuitry, within the integrated circuitry, configured to:
receive a first of the first plurality of signals from the CMOS circuitry;
process the first of the first plurality of signals to generate a first of a second plurality of signals; and
output the first of the second plurality of signals; and
second CMOS circuitry, within the integrated circuit circuitry, configured to:
receive a second of the first plurality of signals from the CMOS circuitry;
process the second of the plurality of signals to generate a second of the second plurality of signals; and
output the second of the second plurality of signals.
14. The apparatus of claim 13 , wherein:
the signal is a serialized signal that has a first frequency;
each of the first plurality of signals has a second frequency that is different than the first frequency; and
each of the second plurality of signals has the second frequency.
15. The apparatus of claim 13 , wherein the C 3 MOS logic is further configured to operate as a flip-flop.
16. The apparatus of claim 13 further comprising:
wherein the C 3 MOS circuitry is coupled to a first power supply voltage;
wherein at least one of: the first CMOS circuitry or the second CMOS circuitry is coupled to a second power supply voltage that is different than the first power supply voltage; and
connecting circuitry between the C 3 MOS circuitry and the at least one of the first CMOS circuitry or the second CMOS circuitry, wherein one of: the connecting circuitry facilitates output of the at least one of the first CMOS circuitry or the second CMOS circuitry being received as input to the CMOS circuitry, or the connecting circuitry facilitates output of the CMOS circuitry being received as input to the at least one of the first CMOS circuitry or the second CMOS circuitry.
17. The apparatus of claim 13 , wherein:
the CMOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein:
a current steering circuit within the CMOS logic including the first source and the second source;
the first source and the second source being coupled together and to a current source;
the first drain and the second drain being coupled to a power supply; and
the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal.