Configurable computing array comprising three-dimensional writable memory
View Patent ↗The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit comprising an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which stores at least a portion of a look-up table (LUT) for a math function.
1. A configurable computing array, comprising:
at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and
at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array stores at least a first portion of a first look-up table (LUT) for a first math function;
wherein said configurable logic element and said configurable computing element are electrically coupled.
2. The configurable computing array according to claim 1 , wherein said first 3D-W array at least partially covers said configurable logic element.
3. The configurable computing array according to claim 1 , further comprising at least a configurable interconnect, wherein said configurable interconnect selectively couples said configurable logic element with said configurable computing element.
4. The configurable computing array according to claim 1 , wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.
5. The configurable computing array according to claim 1 , further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array stores at least a second portion of a second LUT for a second math function.
6. The configurable computing array according to claim 1 , wherein said first 3D-W array is re-programmable and said first configurable computing element can be re-configured to realize different math functions.
7. A configurable computing array, comprising:
at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and
at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array stores at least a first portion of a first look-up table (LUT) for a first math function;
wherein said configurable interconnect and said configurable computing element are electrically coupled.
8. The configurable computing array according to claim 7 , wherein said first 3D-W array at least partially covers said configurable interconnect.
9. The configurable computing array according to claim 7 , further comprising at least a configurable logic element, wherein said configurable logic element selectively couples said configurable interconnect with said configurable computing element.
10. The configurable computing array according to claim 7 , wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.
11. The configurable computing array according to claim 7 , further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array stores at least a second portion of a second LUT for a second math function.
12. The configurable computing array according to claim 7 , wherein said first 3D-W array is re-programmable and said first configurable computing element can be re-configured to realize different math functions.
13. A configurable computing array, comprising:
an array of configurable computing elements including a configurable computing element, wherein said configurable computing element stores at least a portion of a look-up table (LUT) for a math function;
an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;
an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects selectively realizes an interconnect from an interconnect library;
wherein said configurable computing array realizes a math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects.
14. The configurable computing array according to claim 13 , wherein said configurable logic element is formed on said semiconductor substrate.
15. The configurable computing array according to claim 13 , wherein said configurable interconnect is formed on said semiconductor substrate.
16. The configurable computing array according to claim 13 , wherein at least a portion of said configurable computing element is formed in a three-dimensional writable memory (3D-W) array stacked above a semiconductor substrate.
17. The configurable computing array according to claim 14 , wherein said 3D-W array at least partially covers said configurable logic element.
18. The configurable computing array according to claim 14 , wherein said 3D-W array at least partially covers said configurable interconnect.
19. The configurable computing array according to claim 14 , wherein said 3D-W array is re-programmable and said configurable computing element can be re-configured to realize different math functions.
20. The configurable computing array according to claim 13 , further comprising at least one multiplier.