Semiconductor package

1. A semiconductor package, comprising:

a substrate;

a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, the first and second semiconductor chips having facing first side surfaces and second side surfaces opposite to respective ones of the first side surfaces; and

a plurality of bumps having a substantially same size on lower surfaces of respective ones of the first and second semiconductor chips, the plurality of bumps being arranged at a higher density in first regions of respective ones of the first and second semiconductor chips than in second regions of respective ones of the first and second semiconductor chips, the first regions of the first and second semiconductor chips being adjacent to the first side surfaces of the first and second semiconductor chips, respectively, and the second regions of the first and second semiconductor chips being adjacent to the second side surfaces of the first and second semiconductor chips, respectively.

2. The semiconductor package as claimed in claim 1 , wherein the plurality of bumps are arranged in rows and columns on each of the first and second semiconductor chips, each of the first regions being a region in which first bumps of the plurality of bumps are arranged in a column along a corresponding one of the first side surfaces.

3. The semiconductor package as claimed in claim 1 , wherein the plurality of bumps on each of the first and second semiconductor chips have substantially the same size, first bumps of the plurality of bumps in the first regions being arranged at a smaller pitch than second bumps of the plurality of bumps in the second regions.

4. The semiconductor package as claimed in claim 1 , wherein the plurality of bumps are arranged at a gradually decreasing density from the first side surfaces toward corresponding ones of the second side surfaces.

5. The semiconductor package as claimed in claim 1 , further comprising support bumps in the second regions, each one of the support bumps having a greater size than each of the plurality of bumps.

6. The semiconductor package as claimed in claim 1 , further comprising insulating layers between the substrate and each of the first semiconductor chip and the second semiconductor chip, the insulating layers having a higher thermal expansion coefficient than each of the first and second semiconductor chips.

7. The semiconductor package as claimed in claim 6 , wherein the insulating layers are spaced apart from each other between the first and second semiconductor chips.

8. The semiconductor package as claimed in claim 6 , wherein the insulating layers protrude outward from the second side surfaces of the first and second semiconductor chips farther than from respective ones of the first side surfaces.

9. The semiconductor package as claimed in claim 6 , wherein the insulating layers extend from an upper surface of the substrate along the second side surfaces farther than along the first side surfaces.

10. The semiconductor package as claimed in claim 6 , wherein the insulating layers include respective amounts of insulating material on the first and second semiconductor chips in the second regions that are larger than in the first regions.

11. The semiconductor package as claimed in claim 6 , further comprising a molding member covering the first and second semiconductor chips, the molding member having a smaller thermal expansion coefficient than the insulating layers.

12. The semiconductor package as claimed in claim 11 , wherein the substrate contacts the molding member between the first and second semiconductor chips.

13. The semiconductor package as claimed in claim 1 , wherein each of the plurality of bumps includes a pillar portion and a solder portion on the pillar portion.

14. A semiconductor package, comprising:

a substrate;

at least two semiconductor chips on the substrate;

a plurality of bumps on lower surfaces of respective ones of the at least two semiconductor chips, the plurality of bumps being arranged at a higher density in adjacent regions of the at least two semiconductor chips than in other regions of the at least two semiconductor chips; and

at least one insulating layer between the substrate and each of the at least two semiconductor chips to fill between the plurality of bumps, the at least one insulating layer having a height in a region between the at least two semiconductor chips that is smaller than a height on non-adjacent side surfaces of the at least two semiconductor chips.

15. The semiconductor package as claimed in claim 14 , wherein the at least one insulating layer has a higher thermal expansion coefficient than each of the at least two semiconductor chips.

16. A semiconductor package, comprising:

a substrate;

at least two semiconductor chips;

an insulating layer between the substrate and each of the at least two semiconductor chips; and

a plurality of bumps arranged in rows and columns on the at least two semiconductor chips, the plurality of bumps connecting the substrate to the at least two semiconductor chips through the insulating layers,

wherein the plurality of bumps include at least one first column of bumps arranged in a first direction along each of facing edges of the at least two semiconductor chips and at least one second column of bumps arranged in the first direction and farther away from respective ones of the facing edges of the at least two semiconductor chips than the at least one first column of bumps,

wherein first bumps in the at least one first column of bumps are arranged at a higher linear density in the first direction than second bumps in the at least one second column of bumps, and

wherein each of the insulating layers protrudes outward from a respective facing edge of the at least two semiconductor chips less than from a corresponding opposite edge of the at least two semiconductor chips, and without overlapping a lateral side surface of a corresponding one of the at least two semiconductor chips that faces a region between the at least two semiconductor chips.

17. The semiconductor package as claimed in claim 16 , wherein the plurality of bumps have substantially a same size, the first bumps in the at least one first column of bumps being arranged at a smaller pitch than the second bumps in the at least one second column of bumps in the first direction.

18. The semiconductor package as claimed in claim 16 , wherein the plurality of bumps have substantially a same length in a second direction perpendicular to the first direction, each first bump in the at least one first column of bumps has a greater length than each second bump in the at least one second column of bumps in the first direction.