IP Library Granted Patent US 10,788,540
Granted Patent B2
US 10,788,540 · App. 15/796,336 · Granted Sep 29, 2020

Fault detection circuit and related methods

Inventors: Riley Beck (Eagle Mountain, UT); Rishi Pratap Singh (Provo, UT)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G01R31/50G01R31/34H02H1/0007H02H3/16H02H7/08
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Quick Facts
Patent No.
US 10,788,540
App. No.
15/796,336
Granted
Sep 29, 2020
Kind
B2
Abstract

Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

Claims (37)

1. A fault detection circuit comprising:

a first current transformer coupled to a second current transformer;

a positive feedback circuit comprising the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, an inverter, and any combination thereof, all operatively coupled together; and

a plurality of logic gates coupled with the positive feedback circuit;

wherein the positive feedback circuit is configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates;

wherein the plurality of logic gates are configured to analyze the fault signal and open the first switch; and

wherein the plurality of logic gates are further configured to identify whether the fault signal represents one of a true fault and a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

2. The circuit of claim 1 , further comprising a second switch and a third switch, wherein the second switch is configured to open with the first switch.

3. The circuit of claim 1 , wherein the positive feedback circuit further comprises a first gain block and a second gain block, wherein the first gain block and the second gain block are operatively coupled between the first current transformer and the second current transformer.

4. The circuit of claim 1 , wherein the positive feedback circuit further comprises a noise suppression network, the noise suppression network comprising a first capacitor, a second capacitor, a first resistor, and a second resistor operatively coupled together.

5. The circuit of claim 4 , wherein the second resistor is configured to adjust a range of the ground neutral fault detected.

6. The circuit of claim 1 , wherein the fault detection circuit is operatively coupled to a ground fault interrupter (GFI) circuit.

7. The circuit of claim 1 , wherein the fault detection circuit is operatively coupled to a three-phase motor.

8. A fault detection circuit comprising:

a first current transformer coupled to a second current transformer;

a positive feedback circuit comprising the first current transformer, the second current transformer, a first gain block, a second gain block, a first switch, a second switch, a third switch, and a noise suppression network, all operatively coupled together; and

a plurality of logic gates coupled with the positive feedback circuit;

wherein the positive feedback circuit is configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates;

wherein the plurality of logic gates are configured to analyze the fault signal and open the first switch and the second switch and close the third switch; and

wherein the plurality of logic gates are further configured to identify whether the fault signal represents one of a true fault and a noise fault by analyzing the output of the positive feedback circuit after the first switch and the second switch have been opened.

9. The circuit of claim 8 , wherein the plurality of logic gates is further configured to trip a ground fault interrupter (GFI) circuit if the fault signal represents a true fault.

10. The circuit of claim 8 , wherein the circuit is configured to simultaneously detect a ground neutral fault and a normal ground fault.

11. The circuit of claim 8 , wherein the first gain block and the second gain block are coupled between the first current transformer and the first switch, second switch, and third switch.

12. A method for detecting a fault comprising:

providing a first current transformer and a second current transformer, the first current transformer and the second current transformer electrically coupled with a hot line and a neutral line;

detecting a potential fault condition using the second current transformer;

producing an oscillating signal and transmitting the oscillating signal to a plurality of logic gates electrically coupled with the first current transformer and the second current transformer;

opening a switch electrically coupled with the second current transformer in response to a switching signal from the plurality of logic gates; and

determining whether the potential fault condition is a true fault condition by monitoring whether the oscillating signal continues after opening the switch.

13. The method of claim 12 , further comprising sending a signal to trip a ground fault interrupter (GFI) circuit if the oscillating signal dissipates after opening the switch.

14. The method of claim 12 , further comprising closing the switch electrically coupled with the second current transformer to reset the circuit if the oscillating signal continues after opening the switch.

15. The method of claim 12 , further comprising providing a second oscillating signal and third oscillating signal and determining whether the potential fault condition is a true fault condition after the second oscillating signal and the third oscillating signal are transmitted to the plurality of logic gates.

16. The method of claim 12 , further comprising sending a signal to trip a three-phase motor if the oscillating signal dissipates after opening the switch.

17. The method of claim 12 , wherein the oscillating signal is transmitted through a positive feedback circuit, the positive feedback circuit comprising the first current transformer, the second current transformer, a first gain block, a second gain block, the switch, a second switch, a third switch, and a noise suppression network all operatively coupled together.

18. The method of claim 17 , further comprising opening the second switch with the switch in response to a switching signal from the plurality of logic gates and closing the third switch in response to a second switching signal from the plurality of logic gates.

19. The method of claim 12 , wherein detecting the potential fault condition comprises detecting a resistance less than 10 ohms between a return line and a ground.

20. The method of claim 12 , wherein the switch is opened no later than 64 microseconds after the oscillating signal is produced.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0494 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064159/0524 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0494 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2017
From: BECK, RILEY; SINGH, RISHI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044052/0151 →
Continuity (1)
Related Publication 20190128941A1 · May 2, 2019