LOW GATE CURRENT JUNCTION FIELD EFFECT TRANSISTOR DEVICE ARCHITECTURE
A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.
1 . A junction field effect transistor (JFET) comprising:
a first doped region acting as a source region; a second doped region acting as a drain region; a bottom gate; a top gate; and a channel extending between the first and second doped regions;
wherein the top gate is lightly doped and the first and second doped regions are formed such that they touch the top gate or are spaced apart from the top gate by less than twice the depth of the top gate, and where at least a third doped region is formed opposite the second doped region but is separated from the second doped region by the channel and is doped with the same type of dopant as the second doped region.
2 . A JFET as claimed in claim 1 , in which the top gate has a doping concentration similar to or less than that of the bottom gate.
3 . A JFET as claimed in claim 1 , in which the first and second doped regions extend further into the channel than the top gate.
4 . A JFET as claimed in claim 1 , in which the bottom gate has a varying spatial profile such that the separation between the top gate and the bottom gate varies as a function of position.
5 . A JFET as claimed in claim 4 , in which the bottom gate is furthest from the top gate towards an edge of the top gate where the top gate is adjacent the second doped region.
6 . A JFET as claimed in claim 4 , in which the bottom gate has a peripheral portion of substantially uniform depth adjacent a raised portion of the bottom gate.
7 . A JFET as claimed in claim 6 , in which the third doped region extends above the profile of the adjacent section of the bottom gate.
8 . A JFET as claimed in claim 1 , further comprising a fourth doped region formed opposite but separated from the first doped region and doped with the same type of impurity as the first doped region.
9 . A JFET as claimed in claim 1 , in which the third doped region is less heavily doped than the second doped region.
10 . A JFET as claimed in claim 1 , in which gate current due to impact ionization is less than 10% of the gate current due to p-n junction leakage through the gate.
11 . A JFET as claimed in claim 1 , in which the JFET is a junction insulated device formed within a well of semiconductor.
12 . A JFET as claimed in claim 1 , in which the JFET is formed within a well which is defined by dielectric materials.
13 . An integrated circuit including at least one JFET as claimed in claim 1 .
14 . A method of forming a JFET having first, second and third doped regions of a first semiconductor type, the method comprising forming the third region of a first semiconductor type in or adjacent a region of a semiconductor type which in the completed JFET forms a back gate of the JFET; forming a layer of semiconductor of first semiconductor type over the back gate and the third region, the layer of semiconductor being less highly doped than the third region; forming first and second doped regions and a top gate, where the top gate is between the first and second doped regions and the second region is formed above the third region and is separated from the third region by a portion of the layer of semiconductor.
15 . A method as claimed in claim 14 , further comprising forming a fourth doped region of the first semiconductor type in a position that is beneath the source of the completed JFET.
16 . A method as claimed in claim 14 , in which the first and second doped regions are formed by counter-doping regions of the top gate.
17 . A method as claimed in claim 14 , in which the first and second doped regions extend deeper into the JFET than the top gate.
18 . A method as claimed in claim 14 , in which the doping of the top gate is less dense than the doping of the bottom gate.