Structure and method for metal gates with roughened barrier layer

1. A method of forming a semiconductor device, comprising:

receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the substrate and surrounding the gate trench;

forming a gate dielectric layer in the gate trench;

forming a barrier layer in the gate trench and over the gate dielectric layer;

treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and

forming an n-type work function metal layer over the treated barrier layer.

2. The method of claim 1 , wherein the n-type work function metal layer includes aluminum (Al).

3. The method of claim 2 , wherein the barrier layer includes tantalum nitride (TaN) or titanium nitride (TiN).

4. The method of claim 3 , wherein the treating of the barrier layer includes applying a chlorine-containing gas to the barrier layer.

5. The method of claim 4 , wherein the chlorine-containing gas includes tungsten chloride (WCl x ).

6. The method of claim 1 , wherein the outer surface of the barrier layer is roughened to have an average surface roughness (Ra) of 3 to 10 angstroms.

7. The method of claim 1 , wherein the treating of the barrier layer is performed at a temperature ranging from 400 to 500 degrees Celsius and a pressure ranging from 10 to 35 Torr.

8. The method of claim 1 , further comprising:

forming a capping layer between the gate dielectric layer and the barrier layer.

9. A method of forming a semiconductor device, comprising:

receiving a structure having a substrate, first and second gate trenches over the substrate, and a dielectric layer over the substrate and surrounding the first and second gate trenches;

depositing a gate dielectric layer in the first and second gate trenches;

depositing a barrier layer in the first and second gate trenches and over the gate dielectric layer;

depositing a p-type work function metal layer in the first and second gate trenches and over the barrier layer;

forming a patterned mask covering the second gate trench;

removing the p-type work function metal layer from the first gate trench, thereby exposing the barrier layer in the first gate trench;

removing the patterned mask after the removing of the p-type work function metal layer from the first gate trench;

treating the barrier layer in the first gate trench to roughen an outer surface of the barrier layer; and

after the treating of the barrier layer, depositing an n-type work function metal layer in the first and second gate trenches.

10. The method of claim 9 , wherein the treating of the barrier layer and the depositing of the n-type work function metal layer are performed without breaking vacuum.

11. The method of claim 9 , further comprising:

forming a capping layer over the gate dielectric layer before the forming of the barrier layer.

12. The method of claim 9 , wherein the gate dielectric layer includes a high-k dielectric material, the barrier layer includes a metal nitride, and the n-type work function metal layer includes aluminum.

13. The method of claim 9 , further comprising:

depositing a metal blocking layer over the n-type work function metal layer in the first and second gate trenches.

14. The method of claim 9 , wherein the treating of the barrier layer includes applying a metal chloride gas to the barrier layer in the first gate trench.

15. The method of claim 14 , wherein the metal chloride gas includes a tungsten chloride.

16. A semiconductor structure, comprising:

a substrate;

a gate stack over the substrate; and

source and drain features adjacent to the gate stack,

wherein the gate stack includes:

a high-k dielectric layer,

a barrier layer over the high-k dielectric layer, the barrier layer having a roughened surface, and

an n-type work function metal layer over the roughened surface.

17. The semiconductor structure of claim 16 , wherein the roughened surface has an average surface roughness of 3 to 10 angstroms.

18. The semiconductor structure of claim 16 , further comprising a capping layer between the high-k dielectric layer and the barrier layer.

19. The semiconductor structure of claim 18 , wherein each of the n-type work function metal layer and the barrier layer includes aluminum, and wherein the gate stack also includes aluminum between the barrier layer and the capping layer.

20. The semiconductor structure of claim 16 , wherein:

the n-type work function metal layer includes aluminum and titanium; and

the barrier layer includes aluminum and one of titanium nitride and tantalum nitride,

wherein the gate stack further includes aluminum between the barrier layer and the high-k dielectric layer.