Memory system and controller
In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
1. A memory system comprising:
a nonvolatile memory;
a controller circuit configured to receive a write command from a host and control the nonvolatile memory; and
a power control circuit including a battery, the battery being configured to store power supplied from an external supply, the power control circuit being configured to supply, to a component of the memory system, at least one of the power supplied from the external supply and the power stored in the battery, wherein,
if a completion response for the write command has not been returned to the host in a case where the power becomes unsupplied from the external supply, the controller circuit aborts, using the power stored in the battery, the write command received from the host.
2. The memory system according to claim 1 , wherein,
in the case where the power becomes unsupplied from the external supply, the controller circuit further stops accepting a write command from the host.
3. The memory system according to claim 1 , further comprising:
a buffer, wherein,
in the case where the power becomes unsupplied from the external supply, the controller circuit further writes first write data stored in the buffer into the nonvolatile memory using the power stored in the battery, the first write data being data related to a write command received from the host and for which a completion response has been returned to the host.
4. The memory system according to claim 3 , wherein
the nonvolatile memory includes a memory cell, and
the controller circuit writes the first write data into the nonvolatile memory so that the memory cell into which at least a part of the first write data is written records only one bit.
5. The memory system according to claim 3 , wherein
the controller circuit is further configured to conduct address translation from a logical address specified by the host to a physical address in the nonvolatile memory corresponding to the logical address, and,
when the first write data has a size that is less than a minimum unit in which the address translation is conducted, the controller circuit writes the first write data into the nonvolatile memory without conducting a padding process, the padding process being a process in which the first write data is padded with second write data stored in the nonvolatile memory.
6. The memory system according to claim 3 , wherein,
upon a start-up of the memory system after the controller circuit has written the first write data into the nonvolatile memory, the controller circuit reads the first write data from the nonvolatile memory using the power supplied from the external supply, and writes third write data into the nonvolatile memory using the power supplied from the external supply, the third write data being the first write data read from the nonvolatile memory.
7. The memory system according to claim 6 , wherein
the nonvolatile memory includes a memory cell, and
the controller circuit writes the third write data into the nonvolatile memory so that the memory cell into which at least a part of the third write data is written records more than one bit.
8. The memory system according to claim 6 , wherein
the nonvolatile memory includes blocks, each of the blocks being a unit of erasing, and
the controller circuit writes the third write data into a block that is different from a block in which the first write data is stored.
9. The memory system according to claim 1 , wherein
the battery is composed of a capacitor.
10. The memory system according to claim 1 , wherein,
in the case where the power becomes unsupplied from the external supply, the controller circuit aborts the write command when a charge level of the battery is less than a first threshold.
11. A method of controlling a memory system, the memory system including:
a nonvolatile memory;
a controller circuit; and
a power control circuit including a battery, the battery being configured to store power supplied from an external supply, the power control circuit being configured to supply at least one of the power supplied from the external supply and the power stored in the battery to a component of the memory system,
the method executed using the controller circuit, comprising:
if a completion response for a write command has not been returned to a host in a case where the power becomes unsupplied from the external supply, aborting, using the power stored in the battery, the write command received from the host.
12. The method according to claim 11 , further comprising:
in the case where the power becomes unsupplied from the external supply, stopping accepting a write command from the host.
13. The method according to claim 11 , wherein
the memory system further includes a buffer, and
the method further comprises:
in the case where the power becomes unsupplied from the external supply, writing first write data stored in the buffer into the nonvolatile memory using the power stored in the battery the first write data being data related to a write command received from the host and for which a completion response has been returned to the host.
14. The method according to claim 13 , wherein
the nonvolatile memory includes a memory cell, and
the method further comprises:
writing the first write data into the nonvolatile memory so that the memory cell into which at least a part of the first write data is written records only one bit.
15. The method according to claim 13 , further comprising:
conducting address translation from a logical address specified by the host to a physical address in the nonvolatile memory corresponding to the logical address; and,
when the first write data has a size that is less than a minimum unit in which the address translation is conducted, writing the first write data into the nonvolatile memory without conducting a padding process, the padding process being a process in which the first write data is padded with second write data stored in the nonvolatile memory.
16. The method according to claim 13 , further comprising:
upon a start-up of the memory system after having written the first write data into the nonvolatile memory, reading the first write data from the nonvolatile memory using the power supplied from the external supply, and writing third write data into the nonvolatile memory using the power supplied from the external supply, the third write data being the first write data read from the nonvolatile memory.
17. The method according to claim 16 , wherein
the nonvolatile memory includes a memory cell, and
the method further comprises:
writing the third write data into the nonvolatile memory so that the memory cell into which at least a part of the third write data is written records more than one bit.
18. The method according to claim 16 , wherein
the nonvolatile memory includes blocks, each of the blocks being a unit of erasing, and
the method further comprises:
writing the third write data into a block that is different from a block in which the first write data is stored.
19. The method according to claim 11 , wherein
the battery is composed of a capacitor.
20. The method according to claim 11 , further comprising:
in the case where the power becomes unsupplied from the external supply, aborting the write command when a charge level of the battery is less than a first threshold.