Semiconductor device and method for fabricating the same
View Patent ↗A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.
1. A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming a plurality of semiconductor fins on the semiconductor substrate;
forming a solid-state dopant source layer on the semiconductor fins;
forming an insulating buffer layer on the solid-state dopant source layer; and
forming a fin bump between the semiconductor fins, wherein the fin bump comprises a sidewall spacer, wherein the sidewall spacer does not cover a top surface of the fin bump.
2. The method for fabricating a semiconductor device according to claim 1 , further comprising:
forming a dielectric layer on the insulating buffer layer and the fin bump;
recessing the dielectric layer, the insulating buffer layer and the solid-state dopant source layer to a level below a top surface of the semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins; and
driving dopants from the solid-state dopant source layers into the sub-fin regions of each of the plurality of semiconductor fins.
3. The method for fabricating a semiconductor device according to claim 2 , further comprising:
forming a gate electrode traversing the protruding portions of each of the plurality of semiconductor fins;
forming source and drain regions in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate electrode; and
cutting the gate electrode into gate segments.
4. The method for fabricating a semiconductor device according to claim 3 , wherein each of the gate segments has a gate edge that is partially overlapped with the fin bump when viewed from above.
5. The method for fabricating a semiconductor device according to claim 4 , wherein the gate edge does not completely overlap with the fin bump when viewed from above.
6. The method for fabricating a semiconductor device according to claim 1 , wherein the solid-state dopant source layer comprises a borosilicate glass (BSG) layer.
7. The method for fabricating a semiconductor device according to claim 1 , wherein the solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
8. The method for fabricating a semiconductor device according to claim 1 , wherein the insulating buffer layer comprises silicon nitride.
9. The method for fabricating a semiconductor device according to claim 1 , wherein the sidewall spacer comprises a residual portion of the solid-state dopant source layer and a residual portion of the insulating buffer layer.
10. A semiconductor device, comprising:
a semiconductor substrate;
a plurality of semiconductor fins;
a solid-state dopant source layer on the semiconductor substrate,
an insulating buffer layer on the solid-state dopant source layer; and
a first fin bump, wherein the first fin bump comprises a first sidewall spacer, and wherein the first sidewall spacer does not cover a top surface of the fin bump.
11. The semiconductor device according to claim 10 , wherein the solid-state dopant source layer comprises a borosilicate glass (BSG) layer.
12. The semiconductor device according to claim 10 , wherein the solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
13. The semiconductor device according to claim 10 , wherein the insulating buffer layer comprises silicon nitride.
14. The semiconductor device according to claim 10 , wherein the first sidewall spacer comprises a residual portion of the solid-state dopant source layer and a residual portion of the insulating buffer layer.
15. The semiconductor device according to claim 10 further comprises a recessed region in the semiconductor substrate and next to the first fin bump.
16. The semiconductor device according to claim 15 , wherein the recessed region is filled with a dielectric layer.
17. The semiconductor device according to claim 16 further comprises a gate segment on the dielectric layer and a gate edge of the gate segment that is partially overlapped with the first fin bump.
18. The semiconductor device according to claim 10 , wherein the first sidewall spacer has a top surface that is higher than the top surface of the first fin bump.
19. The semiconductor device according to claim 10 further comprises a second fin bump, wherein the second fin bump comprises a second sidewall spacer that has different structure from the first sidewall spacer.