Automated boot failure prevention and recovery circuit and related method
An automated boot failure prevention and recovery circuit includes one or more non-transitory computer-readable media having computer-executable instructions embodied thereon, a processor coupled to the one or more non-transitory computer-readable media, and configured to execute the computer-executable instructions to electrically disconnect a memory from a power source, short the memory to ground for a predetermined period of time to adjust memory content from a stochastic state to a machine-tolerable state or an acceptable non-failure state. The processor is further configured to execute the computer-executable instructions to electrically disconnect the memory from the ground, and electrically reconnect the memory to the power source. The processor is further configured to execute the computer-executable instructions to apply a load across the power source, acquire power source information, and notify the user of the battery charge status to preclude loss of memory data.
1. An automated boot failure prevention and recovery circuit, comprising:
one or more non-transitory computer-readable media having computer-executable instructions embodied thereon;
at least one processor coupled to the one or more non-transitory computer-readable media, and configured to execute the computer-executable instructions to:
electrically disconnect a memory from a power source;
short the memory to ground for a predetermined period of time while the memory is electrically disconnected from the power source in order to adjust memory content from a stochastic state to a machine-tolerable state or an acceptable non-failure state;
apply a load across the power source; and
acquire power source information.
2. The automated boot failure prevention and recovery circuit of claim 1 , wherein shorting the memory to the ground rewrites memory cells to predefined states.
3. The automated boot failure prevention and recovery circuit of claim 1 , wherein:
the at least one processor is further configured to execute the computer-executable instructions to:
electrically disconnect the memory from the ground; and
electrically reconnect the memory to the power source.
4. The automated boot failure prevention and recovery circuit of claim 1 , wherein the memory is a static random access memory (SRAM).
5. The automated boot failure prevention and recovery circuit of claim 1 , wherein the automated boot failure prevention and recovery circuit is on a motherboard of an electronic computing device.
6. The automated boot failure prevention and recovery circuit of claim 1 , wherein the memory contains system firmware of an electronic computing device.
7. A method for preventing or recovering from a boot failure in a logic board, the method comprising:
electrically disconnecting a memory from a power source;
shorting the memory to ground for a predetermined period of time while the memory is electrically disconnected from the power source in order to adjust memory content from a stochastic state to a machine-tolerable state or an acceptable non-failure state;
applying a load across the power source; and
acquiring power source information.
8. The method of claim 7 further comprising:
electrically disconnecting the memory from the ground; and
electrically reconnecting the memory to the power source.
9. The method of claim 7 , wherein the memory is a static random access memory (SRAM).
10. The method of claim 7 , wherein the logic board is a motherboard of an electronic computing device.
11. The method of claim 7 , wherein the memory contains system firmware of an electronic computing device.
12. An electronic device, comprising:
a battery;
a static random access memory (SRAM);
an automated boot failure prevention and recovery circuit coupled between the battery and the SRAM,
wherein the automated boot failure prevention and recovery circuit comprises:
one or more non-transitory computer-readable media having computer-executable instructions embodied thereon;
at least one processor coupled to the one or more non-transitory computer-readable media, and configured to execute the computer-executable instructions to:
electrically disconnect the SRAM from the battery;
short the SRAM to ground for a predetermined period of time while the memory is electrically disconnected from the battery in order to adjust content of the SRAM from a stochastic state to a machine-tolerable state or an acceptable non-failure state;
apply a load across the battery; and
acquire battery information.
13. The electronic device of claim 12 , wherein shorting the SRAM to the ground rewrites memory cells in the SRAM to predefined states.
14. The electronic device of claim 12 , wherein:
the at least one processor is further configured to execute the computer-executable instructions to:
electrically disconnect the SRAM from the ground; and
electrically reconnect the SRAM to the battery.
15. The electronic device of claim 12 , wherein:
the automated boot failure prevention and recovery circuit further comprises a switch; and
the at least one processor is configured to execute the computer-executable instructions to send a signal to open the switch to electrically disconnect the SRAM from the battery.
16. The electronic device of claim 12 , wherein:
the boot failure prevention control circuit further comprises a switch; and
the at least one processor is configured to execute the computer-executable instructions to send a signal to close the switch to short the SRAM to the ground.
17. The electronic device of claim 12 , wherein:
the automated boot failure prevention and recovery circuit further comprises a switch; and
the at least one processor is configured to execute the computer-executable instructions to send a signal to close the switch to apply the load across the battery.