Lossy MIM capacitor for on-die noise reduction
According to certain aspects of the present disclosure, a semiconductor die includes a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die, a first supply rail formed from the second interconnect metal layer, and a resistive metal path coupled between the decoupling capacitor and the first supply rail. The decoupling capacitor may be a metal-insulator-metal (MIM) capacitor. In some embodiments, the resistive metal path includes a plurality of elongated segments, and one or more connecting segments, wherein each of the one or more connecting segments electrically couples a respective pair of the plurality of elongated segments. In some embodiments, the resistive metal path includes multiple vias coupled in series.
1. A semiconductor die, comprising:
a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die;
a first supply rail formed from the second interconnect metal layer; and
a resistive metal path coupled between the decoupling capacitor and the first supply rail, wherein the resistive metal path comprises:
a first interconnect coupled to the decoupling capacitor;
a second interconnect below the first interconnect and the first supply rail;
a first path comprising a first plurality of vias coupled in series, wherein the first path is coupled between the first interconnect and the second interconnect; and
a second path comprising a second plurality of vias coupled in series, wherein the second path is coupled between the first supply rail and the second interconnect.
2. The semiconductor die of claim 1 , wherein the decoupling capacitor comprises:
a first metal plate;
a second metal plate; and
an insulator layer between the first and second metal plates;
wherein the resistive metal path is coupled between the first metal plate and the first supply rail.
3. The semiconductor die of claim 2 , further comprising a second supply rail, wherein a second metal plate is coupled to the second supply rail.
4. The semiconductor die of claim 1 , wherein the first interconnect comprises a winding path comprising:
a plurality of elongated segments; and
one or more connecting segments, wherein each of the one or more connecting segments electrically couples a respective pair of the plurality of elongated segments, and the winding path is coupled in series with the first plurality of vias.
5. The semiconductor die of claim 4 , wherein the plurality of elongated segments are orientated along a first lateral direction, the one or more connecting segments are orientated along a second lateral direction, and the first lateral direction is approximately perpendicular to the second lateral direction.
6. The semiconductor die of claim 1 , wherein the first and second interconnect metal layers are separated vertically from a front end of line (FEOL) of the die by at least five intervening interconnect metal layers of the die.
7. The semiconductor die of claim 1 , wherein the second interconnect is separated vertically from the first interconnect by at least one intervening metal interconnect layer of the die.
8. The semiconductor die of claim 1 , further comprising a via coupled between the decoupling capacitor and the first interconnect.
9. The semiconductor die of claim 1 , wherein the decoupling capacitor comprises a metal-insulator-metal (MIM) capacitor.
10. The semiconductor die of claim 1 , wherein the first plurality of vias comprises at least three vias coupled in series.
11. A semiconductor die, comprising:
a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die, wherein the decoupling capacitor comprises multiple capacitors coupled in parallel;
a first supply rail formed from the second interconnect metal layer, wherein the first supply rail is coupled to the decoupling capacitor;
a second supply rail formed from the first interconnect metal layer;
a third supply rail formed from the second interconnect metal layer; and
a plurality of vias between two of the multiple capacitors, wherein each of the plurality of vias is coupled between the second supply rail and the third supply rail.
12. The semiconductor die of claim 11 , further comprising a resistive path coupled between the decoupling capacitor and the first supply rail.
13. The semiconductor die of claim 12 , wherein the resistive path comprises a plurality of vias coupled in series.
14. The semiconductor die of claim 12 , wherein the resistive path comprises:
a plurality of elongated segments; and
one or more connecting segments, wherein each of the one or more connecting segments electrically couples a respective pair of the plurality of elongated segments.
15. The semiconductor die of claim 11 , wherein the first and second interconnect metal layers are separated vertically from a front end of line (FEOL) of the die by at least five intervening interconnect metal layers of the die.
16. The semiconductor die of claim 11 , wherein the multiple capacitors comprise multiple metal-insulator-metal (MIM) capacitors.
17. The semiconductor die of claim 11 , wherein:
each of the multiple capacitors comprises a respective metal plate;
the decoupling capacitor comprises a plurality of metal traces electrically coupling the metals plates of the multiple capacitors; and
the metal traces and the metal plates of the multiple capacitors are formed from a same metal layer.