Photodiode gate dielectric protection layer
In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.
1. A method of forming an integrated chip, comprising:
forming a gate dielectric layer over a substrate;
selectively forming a gate material over the gate dielectric layer;
forming a gate dielectric protection layer over the gate dielectric layer and the gate material;
forming a masking layer over the gate dielectric layer, wherein sidewalls of the gate dielectric protection layer protrude vertically outward past an upper surface of the masking layer that faces away from the gate dielectric layer;
etching the gate dielectric protection layer according to the masking layer; and
forming a first sidewall spacer over the gate dielectric protection layer and flanking a side of the gate material after etching the gate dielectric protection layer, wherein the gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.
2. The method of claim 1 , further comprising:
forming a photodiode within the substrate, wherein the gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to directly over the photodiode.
3. The method of claim 1 , further comprising:
using one or more implantation processes to form a photodiode within the substrate after formation of the gate dielectric protection layer, wherein the gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to directly over the photodiode.
4. The method of claim 1 , wherein the gate dielectric protection layer comprises an oxide, a nitride, or a high-k dielectric material.
5. The method of claim 1 , further comprising:
selectively forming a hard mask over the gate material, wherein the first sidewall spacer is laterally adjacent to the hard mask.
6. The method of claim 1 , wherein the masking layer directly contacts sidewalls of the gate dielectric protection layer on opposing sides of the gate material.
7. The method of claim 1 , further comprising:
forming a second masking layer over the substrate;
implanting one or more dopant species into the substrate according to the second masking layer; and
removing the second masking layer from over the substrate, wherein a thickness of the gate dielectric protection layer is reduced by way of an etching process that removes the second masking layer.
8. The method of claim 1 , wherein the gate dielectric protection layer has a first thickness below the first sidewall spacer and a maximum second thickness outside of the first sidewall spacer, wherein the first thickness is larger than the maximum second thickness.
9. The method of claim 1 , wherein the gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate material.
10. A method of forming an integrated chip, comprising:
forming a gate dielectric layer over a substrate;
forming a gate structure over the gate dielectric layer;
forming a gate dielectric protection layer over the gate dielectric layer;
forming sidewalls spacers along sides of the gate structure and over a part of the gate dielectric protection layer; and
reducing a thickness of the gate dielectric protection layer that is outside of the sidewall spacers to a non-zero thickness.
11. The method of claim 10 , further comprising:
forming a photodiode within the substrate, wherein the gate dielectric protection layer continuously extends from directly over the photodiode to between the sidewall spacers and the gate dielectric layer.
12. The method of claim 10 , wherein forming the gate dielectric protection layer, comprises:
forming a conformal dielectric layer over the substrate;
forming a first masking layer over a first part of the conformal dielectric layer; and
removing a second part of the conformal dielectric layer not covered by the first masking layer to form the gate dielectric protection layer.
13. The method of claim 10 , wherein the gate dielectric protection layer has a first thickness below the sidewall spacers and a maximum second thickness outside of the sidewall spacers, wherein the first thickness is larger than the maximum second thickness.
14. The method of claim 10 , wherein the gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.
15. The method of claim 10 , further comprising:
forming a masking layer over the substrate;
implanting one or more dopant species into the substrate according to the masking layer; and
removing the masking layer from over the substrate, wherein the thickness of the gate dielectric protection layer is reduced by way of an etching process that removes the masking layer.
16. The method of claim 10 , further comprising:
forming a photoresist layer over the substrate;
implanting one or more dopant species into the substrate according to the photoresist layer; and
removing the photoresist layer from over the substrate, wherein the thickness of the gate dielectric protection layer is reduced by way of an ashing process that removes the photoresist layer.
17. A method of forming an integrated chip, comprising:
forming a conductive gate material over a substrate;
forming a gate dielectric protection layer over the substrate;
forming sidewalls spacers along sides of the conductive gate material and over the gate dielectric protection layer; and
reducing a thickness of the gate dielectric protection layer not covered by the sidewall spacers to a non-zero thickness.
18. The method of claim 17 , wherein forming the gate dielectric protection layer, comprises:
forming a conformal dielectric layer over the substrate; and
removing the conformal dielectric layer from a top of the conductive gate material to form the gate dielectric protection layer.
19. The method of claim 17 , further comprising:
forming a masking layer over the substrate;
implanting one or more dopant species into the substrate according to the masking layer; and
removing the masking layer from over the substrate, wherein the thickness of the gate dielectric protection layer is reduced by way of an etching process that removes the masking layer.
20. The method of claim 19 , wherein the masking layer comprises photoresist.