MULTI-NODE TESTING SYSTEM AND METHOD
An automated microtester array, for simultaneously testing a plurality of devices under test, includes a plurality of automated microtesters, wherein each of the plurality of automated microtesters is configured to test a plurality of devices under test. A central computing system is configured to automate the testing of the plurality of devices under test coupled to the plurality of automated microtesters. A method and computer program product for instructing a plurality of automated microtesters to load an automated test process; and instructing the plurality of automated microtesters in execute the automated test process.
1 . An automated microtester array, for simultaneously testing a plurality of devices under test, comprising:
a plurality of automated microtesters, wherein each of the plurality of automated microtesters is configured to test a plurality of devices under test; and
a central computing system configured to automate the testing of the plurality of devices under test coupled to the plurality of automated microtesters.
2 . The automated microtester array of claim 1 wherein the central computing system is configured to execute an automated array process.
3 . The automated microtester array of claim 2 wherein the automated array process is configured to control the plurality of automated microtesters.
4 . The automated microtester array of claim 2 wherein the automated array process is configured to simultaneously test each of the plurality of devices under test.
5 . The automated microtester array of claim 1 wherein each of the plurality of automated microtesters includes:
a processing system including a plurality of processor assemblies;
a plurality of test sites configured to releasably engage the plurality of devices under test; and
an instrumentation system that is controllable by the processing system and configured to provide one or more input signals to the plurality of test sites and read one or more monitored signals from the plurality of test sites.
6 . The automated microtester array of claim 5 wherein the processing system includes:
a multicore processor.
7 . The automated microtester array of claim 6 wherein the plurality of processor assemblies included within the processing system includes:
a plurality of processor cores included within the multicore processor.
8 . The automated microtester array of claim 5 wherein the plurality of test sites are configured to receive a plurality of adapter boards.
9 . The automated microtester array of claim 8 wherein the plurality of adapter boards are configured to releasably receive the plurality of devices under test.
10 . The automated microtester array of claim 5 wherein the processing system is configured to execute an automated test process.
11 . The automated microtester array of claim 10 wherein the automated test process is configured to control the instrumentation system and define the one or more input signals provided to the plurality of test sites and the one or more monitored signals read from the plurality of test sites.
12 . The automated microtester array of claim 10 wherein the automated test process is configured to simultaneously test each of the plurality of devices under test.
13 . A computer implemented method, executed on a computing device, comprising:
instructing a plurality of automated microtesters to load an automated test process; and
instructing the plurality of automated microtesters in execute the automated test process.
14 . The computer implemented method of claim 13 further comprising:
receiving waveforms and measurements from the plurality of automated microtesters.
15 . The computer implemented method of claim 14 wherein the waveforms and measurements include one or more of:
one or more input signals provided to a plurality of test sites included within the plurality of automated microtesters; and
one or more monitored signals read from the plurality of test sites.
16 . The computer implemented method of claim 14 further comprising:
receiving one or more end-on-test indicators concerning the automated test process executed on the plurality of automated microtesters.
17 . A computer program product residing on a computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
instructing a plurality of automated microtesters to load an automated test process; and
instructing the plurality of automated microtesters in execute the automated test process.
18 . The computer program product of claim 17 further comprising:
receiving waveforms and measurements from the plurality of automated microtesters.
19 . The computer program product of claim 18 further comprising:
receiving one or more end-on-test indicators concerning the automated test process executed on the plurality of automated microtesters.