Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers

1. A method for fabricating a semiconductor device, comprising:

forming a semiconductor fin on a surface of a semiconductor substrate;

epitaxially growing a lower source/drain region on the surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region is formed of a first type of epitaxial semiconductor material;

epitaxially growing a sacrificial epitaxial semiconductor layer on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material;

selectively oxidizing the sacrificial epitaxial semiconductor layer to form a self-aligned bottom insulating spacer comprising an oxide layer; and

forming a gate structure in contact with sidewalls of the semiconductor fin;

wherein the self-aligned bottom insulating spacer electrically insulates the gate structure from the lower source/drain region; and

wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium which is greater than the first concentration of germanium.

2. A method for fabricating a semiconductor device, comprising:

forming a semiconductor fin on a surface of a semiconductor substrate;

epitaxially growing a lower source/drain region on the surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region is formed of a first type of epitaxial semiconductor material;

epitaxially growing a sacrificial epitaxial semiconductor layer on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material;

selectively oxidizing the sacrificial epitaxial semiconductor layer to form a self-aligned bottom insulating spacer comprising an oxide layer;

forming a gate structure in contact with sidewalls of the semiconductor fin;

wherein the self-aligned bottom insulating spacer electrically insulates the gate structure from the lower source/drain region; and

forming a high-concentration germanium semiconductor layer between the oxide layer and the lower source/drain region, wherein the high-concentration germanium semiconductor layer is formed as a result of the selective oxidation process which pushes germanium atoms in the sacrificial epitaxial semiconductor layer towards the lower source/drain region.

3. The method of claim 1 , wherein the oxide layer comprises a silicon oxide layer which is formed by selectively oxidizing the second type of epitaxial semiconductor material using one of a radical oxidation process and a low temperature thermal oxidation process.

4. The method of claim 2 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium.

5. The method of claim 2 , further comprising:

forming an opening in a portion of the self-aligned bottom insulating spacer to expose a portion of the high-concentration germanium semiconductor layer;

etching the exposed portion of the high-concentration germanium semiconductor layer selective to the self-aligned bottom insulating spacer and the lower source/drain region to form a lateral opening in the high-concentration germanium semiconductor layer between the self-aligned bottom insulating spacer and the lower source/drain region; and

filling the lateral opening with a conductive material to form lower contact element of a vertical source/drain contact in contact with the lower source/drain region.

6. The method of claim 1 , further comprising:

forming an upper insulating spacer on the gate structure; and

forming an upper source/drain region on an upper portion of the semiconductor fin;

wherein the upper insulating spacer electrically insulates the gate structure from the upper source/drain region.

7. The method of claim 1 , wherein the gate structure comprises a high-k gate dielectric layer and a metallic gate electrode layer.

8. A method for fabricating a semiconductor device, comprising:

patterning a surface of a semiconductor substrate to form a semiconductor fin;

forming sidewall spacers on sidewalls of the semiconductor fin;

recessing the surface of the semiconductor substrate to a target depth below a bottom level of the sidewall spacers to form an extended bottom portion of the semiconductor fin;

laterally etching exposed sidewalls of the extended bottom portion of the semiconductor fin to reduce a width of the extended bottom portion of the semiconductor fin;

epitaxially growing a lower source/drain region on the recessed surface of the semiconductor substrate in contact with the extended bottom portion of the semiconductor fin, wherein the lower source/drain region is formed of a first type of epitaxial semiconductor material;

epitaxially growing a sacrificial epitaxial semiconductor layer on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material;

selectively oxidizing the sacrificial epitaxial semiconductor layer to form a self-aligned bottom insulating spacer comprising an oxide layer;

removing the sidewall spacers from the sidewalls of the semiconductor fin; and

forming a gate structure in contact with the sidewalls of the semiconductor fin;

wherein the self-aligned bottom insulating spacer electrically insulates the gate structure from the lower source/drain region.

9. The method of claim 8 , wherein the lower source/drain region is formed with a thickness such that an upper surface of the lower source/drain region is disposed below the bottom level of the sidewall spacers, and wherein the sacrificial epitaxial semiconductor layer is formed with a thickness such that an upper surface the sacrificial epitaxial semiconductor layer is disposed above the bottom level of the sidewall spacers.

10. The method of claim 8 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium.

11. The method of claim 8 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium which is greater than the first concentration of germanium.

12. The method of claim 8 , wherein the oxide layer comprises a silicon oxide layer which is formed by selectively oxidizing the second type of epitaxial semiconductor material using one of a radical oxidation process and a low temperature thermal oxidation process.

13. The method of claim 8 , further comprising forming a high-concentration germanium semiconductor layer between the oxide layer and the lower source/drain region, wherein the high-concentration germanium semiconductor layer is formed as a result of the selective oxidation process which pushes germanium atoms in the sacrificial epitaxial semiconductor layer towards the lower source/drain region.

14. The method of claim 13 , further comprising:

forming an opening in a portion of the self-aligned bottom insulating spacer to expose a portion of the high-concentration germanium semiconductor layer;

etching the exposed portion of the high-concentration germanium semiconductor layer selective to the self-aligned bottom insulating spacer and the lower source/drain region to form a lateral opening in the high-concentration germanium semiconductor layer between the self-aligned bottom insulating spacer and the lower source/drain region; and

filling the lateral opening with a conductive material to form lower contact element of a vertical source/drain contact in contact with the lower source/drain region.

15. The method of claim 8 , further comprising:

forming an upper insulating spacer on the gate structure; and

forming an upper source/drain region on an upper portion of the semiconductor fin;

wherein the upper insulating spacer electrically insulates the gate structure from the upper source/drain region.

16. A semiconductor device, comprising:

a vertical field effect transistor (FET) device on a semiconductor substrate, wherein the vertical FET device comprises:

a semiconductor fin formed on a recessed surface of a semiconductor substrate;

a lower source/drain region formed on the recessed surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region comprises a first type of epitaxial semiconductor material;

a self-aligned bottom insulating spacer formed on the lower source/drain region, the self-aligned bottom insulating spacer comprising an oxide layer formed from oxidation of a second type of epitaxial semiconductor material epitaxially grown on the lower source/drain region, which is different from the first type of epitaxial semiconductor material;

a gate structure formed in contact with sidewalls of the semiconductor fin;

an upper insulating spacer formed on the gate structure;

an upper source/drain region formed on an upper portion of the semiconductor fin; and

a high-concentration germanium semiconductor layer disposed between the oxide layer of the self-aligned bottom insulating spacer and the lower source/drain region;

wherein the self-aligned bottom insulating spacer electrically insulates the lower source/drain region from the gate structure; and

wherein the upper insulating spacer electrically insulates the upper source/drain region from the gate structure.

17. The semiconductor device of claim 16 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium.

18. A semiconductor device, comprising:

a vertical field effect transistor (FET) device on a semiconductor substrate, wherein the vertical FET device comprises:

a semiconductor fin formed on a recessed surface of a semiconductor substrate;

a lower source/drain region formed on the recessed surface of the semiconductor substrate in contact with a bottom portion of the semiconductor fin, wherein the lower source/drain region comprises a first type of epitaxial semiconductor material;

a self-aligned bottom insulating spacer formed on the lower source/drain region, the self-aligned bottom insulating spacer comprising an oxide layer formed from oxidation of a second type of epitaxial semiconductor material epitaxially grown on the lower source/drain region, which is different from the first type of epitaxial semiconductor material;

a gate structure formed in contact with sidewalls of the semiconductor fin;

an upper insulating spacer formed on the gate structure; and

an upper source/drain region formed on an upper portion of the semiconductor fin;

wherein the self-aligned bottom insulating spacer electrically insulates the lower source/drain region from the gate structure;

wherein the upper insulating spacer electrically insulates the upper source/drain region from the gate structure; and

wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium that is greater than the first concentration of germanium.

19. The method of claim 2 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium which is greater than the first concentration of germanium.

20. The device of claim 16 , wherein the first type of epitaxial semiconductor material comprises crystalline silicon germanium with a first concentration of germanium, and wherein the second type of epitaxial semiconductor material comprises crystalline silicon germanium with a second concentration of germanium which is greater than the first concentration of germanium.