Semiconductor device

1. A semiconductor device, comprising:

channel patterns disposed on a substrate;

a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and

a gate electrode disposed around the channel patterns,

wherein an interface where the gate electrode meets an overlapping gate capping pattern is recessed between adjacent channel patterns,

wherein the channel patterns are spaced apart from the substrate, and

wherein the gate electrode is disposed between the substrate and the channel patterns.

2. The semiconductor device of claim 1 , further comprising:

a contact connected to at least one of the source/drain patterns,

wherein a lowest point of a top surface of the gate electrode is lower than a bottom surface of the contact.

3. The semiconductor device of claim 1 , wherein the channel patterns are spaced apart from each other and are arranged in a first direction, and

wherein the gate electrode extends in the first direction.

4. The semiconductor device of claim 1 , wherein a first recessed top surface of the gate electrode is disposed between the adjacent channel patterns, a height of the first recessed top surface decreases and then increases from a first channel pattern of the adjacent channel patterns to a second channel pattern of the adjacent channel patterns.

5. The semiconductor device of claim 1 , wherein the substrate includes a first region and a second region,

wherein the source/drain patterns include: first source/drain patterns on the first region; and second source/drain patterns on the second region, and

wherein the first source/drain patterns include a semiconductor element different from a semiconductor element of the substrate.

6. The semiconductor device of claim 5 , wherein the gate electrode includes a first recessed top surface between the adjacent channel patterns, and a second recessed top surface between the first and second regions, and

wherein a height of the second recessed top surface from the substrate is lower than a height of the first recessed top surface from the substrate.

7. The semiconductor device of claim 1 , wherein the source/drain patterns are spaced apart from the substrate,

the semiconductor device further comprising:

insulating patterns disposed between the substrate and the source/drain patterns.

8. The semiconductor device of claim 1 , further comprising:

mask patterns overlapping the channel patterns.

9. The semiconductor device of claim 8 , wherein a highest point of the gate electrode is lower than top surfaces of the mask patterns.

10. The semiconductor device of claim 8 , further comprising:

the gate capping pattern covering the gate electrode and the mask patterns; and

a gate spacer disposed on a sidewall of the gate electrode, an edge portion of each of the mask patterns in a direction perpendicular to an extending direction of the gate electrode, and a sidewall of the gate capping pattern,

wherein a top surface of the gate spacer is substantially coplanar with a top surface of the gate capping pattern.

11. The semiconductor device of claim 1 , wherein the gate electrode is disposed around a top surface, first and second sidewalls and a bottom surface of each of the channel patterns.

12. The semiconductor device of claim 1 , wherein each of the channel patterns includes: a lower channel pattern; and an upper channel pattern spaced apart from the lower channel pattern.

13. A semiconductor device, comprising:

a first channel pattern disposed between a pair of source/drain patterns on a substrate;

a gate electrode disposed around the first channel pattern;

a mask pattern on the first channel pattern; and

a gate capping pattern covering the gate electrode and directly contacting the mask pattern,

wherein a top surface of the gate electrode is lower than a top surface of the mask pattern and is recessed between the first channel pattern and a second channel pattern adjacent to the first channel pattern,

wherein the first channel pattern is spaced apart from the substrate, and

wherein the gate electrode is disposed between the substrate and the first channel pattern.

14. The semiconductor device of claim 13 , further comprising:

a contact connected to the source/drain pattern,

wherein a lowest point of the top surface of the gate electrode is lower than a bottom surface of the contact.

15. A semiconductor device, comprising:

a substrate;

first and second semiconductor patterns disposed on the substrate;

first and second channels disposed on the first and second semiconductor patterns, respectively, wherein the first and second channels are adjacent to each other; and

a gate electrode disposed on first and second sides of each of the first and second channels and between the first semiconductor pattern and the first channel and between the second semiconductor pattern and the second channel,

wherein the gate electrode between the first and second channels is recessed with respect to a mask pattern disposed on each of the first and second channels.

16. The semiconductor device of claim 15 , wherein the first and second channels are fin channels.

17. The semiconductor device of claim 15 , further comprising a contact disposed on a source/drain pattern.

18. The semiconductor device of claim 17 , wherein a surface of the gate electrode between the first and second channels is lower than a bottom surface of the contact.

19. The semiconductor device of claim 15 , wherein the gate electrode surrounds the first and second channels.

20. The semiconductor device of claim 15 , wherein the mask pattern is disposed on a top surface of each of the first and second channels.