Replacement metal gate scheme with self-alignment gate for vertical field effect transistors

1. A method of forming a semiconductor structure, the method comprising:

forming a fin structure over a substrate;

forming a dummy gate over the fin structure;

etching the dummy gate by a first amount to expose a top portion of the fin structure;

forming a first dielectric layer adjacent the exposed top portion of the fin structure;

forming a spacer adjacent the first dielectric layer contacting the fin structure;

etching the dummy gate by a second amount;

depositing a second dielectric layer to encapsulate the remaining dummy gate;

depositing an inter-level dielectric (ILD) over the second dielectric layer;

depositing at least one hard mask to access the dummy gate;

stripping the dummy gate to form at least one recess; and

filling the at least one recess with a high-k metal gate (HKMG).

2. The method of claim 1 , wherein the dummy gate is laterally etched.

3. The method of claim 1 , wherein the HKMG directly contacts the fin structure.

4. The method of claim 1 , further comprising forming a hard mask over the top portion of the fin structure before forming the dummy gate over the fin structure.

5. The method of claim 4 , wherein, after formation of the HKMG, the dummy gate is etched by a third amount to remove the hard mask formed over the top portion of the fin structure.

6. The method of claim 5 , wherein the hard mask is etched to expose the top portion of the fin structure.

7. The method of claim 6 , wherein an epitaxial growth layer is formed directly over the top portion of the fin structure.

8. The method of claim 7 , wherein, after formation of the epitaxial growth layer, a gate contact, source contact, and a drain contact are formed.

9. The method of claim 1 , wherein stripping of the dummy gate results in removal of dielectric adjacent the fin structure.

10. The method of claim 9 , wherein the dummy gate is stripped by wets like hot ammonia.