High density nanosheet diodes
Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.
1. A semiconductor structure, comprising:
a substrate having a field-effect transistor region and a diode region;
a first stack comprising layers of a first material at the field-effect transistor region;
a second stack comprising the layers of the first material alternating with layers of a second material at the diode region, the second material having a first dopant at the diode region, wherein the second material having the first dopant wraps around each of the layers of the first material at the diode region and the second material is directly below a bottommost layer of the layers of the first material at the diode region, wherein the first material at the diode region has a second dopant;
a third material having a third dopant at opposing sidewalls of the second stack, wherein a conductivity type of the first material having the second dopant is the same as a conductivity type of the third material having the third dopant, wherein a conductivity type of the second material having the first dopant is opposite to the conductivity type of the first material having the second dopant and the conductivity type of the third material having the third dopant; and
a metalizing contact material over the substrate, wherein both the field-effect transistor region and the diode region include terminals.
2. The semiconductor structure of claim 1 , further comprising a dielectric layer over the substrate.
3. The semiconductor structure of claim 2 , wherein the dielectric layer is patterned to form trenches.
4. The semiconductor structure of claim 3 , wherein the metalizing contact material fills the trenches.
5. The semiconductor structure of claim 1 , wherein each of the layers of the first material comprises a nanosheet.
6. The semiconductor structure of claim 1 , wherein each of the layers of the first material comprises a nanowire.
7. The semiconductor structure of claim 1 , wherein the first material comprises silicon (Si).
8. The semiconductor structure of claim 1 , wherein the substrate comprises a semiconductor-on-insulator (SOI) structure.
9. The semiconductor structure of claim 1 , wherein the conductivity type of the second material having the first dopant comprises p-type and wherein each of the conductivity type of the first material having the second dopant and the conductivity type of the third material having the third dopant comprises n-type.