Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs
A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.
1. A neuromorphic multi-bit digital weight cell configured to store a plurality of potential weights for a neuron in an artificial neural network, the neuromorphic multi-bit digital weight cell comprising:
a parallel cell comprising:
a plurality of passive resistors in parallel, wherein each passive resistor of the plurality of passive resistors is an un-gated FinFET having an n-doped channel and n+ doped source and drain regions; and
a plurality of gating transistors, each gating transistor of the plurality of gating transistors being in series with one passive resistor of the plurality of passive resistors;
a plurality of programming input lines connected to the plurality of gating transistors;
an input terminal connected to the parallel cell; and
an output terminal connected to the parallel cell.
2. The neuromorphic weight cell of claim 1 , wherein a doping concentration of each of the un-gated FinFETs is between approximately 10 18 cm −3 and approximately 10 19 cm −3 , and wherein each of the un-gated FinFETs is doped with As or P doping.
3. The neuromorphic weight cell of claim 1 , wherein a channel length of each of the un-gated FinFETs is approximately 30 nm, and wherein a doping concentration of each of the un-gated FinFETs is approximately 6*10 18 cm −3 .
4. The neuromorphic weight cell of claim 1 , wherein an overall length of each of the un-gated FinFETs spans more than one contacted poly pitch (CPP).
5. The neuromorphic weight cell of claim 4 , wherein each passive resistor of the plurality of passive resistors comprises a plurality of un-gated FinFETs.
6. The neuromorphic weight cell of claim 1 , wherein each gating transistor of the plurality of gating transistors is a standard core logic transistor.
7. The neuromorphic weight cell of claim 6 , wherein the standard core logic transistor is a FinFET or a gate-all-around field effect transistor (GAA FET).
8. The neuromorphic weight cell of claim 1 , wherein each gating transistor of the plurality of gating transistors is a ferroelectric FET (FeFET), the FeFET comprising a ferroelectric capacitor (FeCap) and an underlying FET, wherein the FeCap is connected to a gate of the underlying FET.
9. A neuromorphic multi-bit digital weight cell configured to store a plurality of potential weights for a neuron in an artificial neural network, the neuromorphic multi-bit digital weight cell comprising:
a parallel cell comprising:
a plurality of passive resistors in parallel, each passive resistor of the plurality of passive resistors having a non-programmable fixed resistance; and
a plurality of gating transistors, each gating transistor of the plurality of gating transistors being in series with one passive resistor of the plurality of passive resistors;
a plurality of programming input lines connected to the plurality of gating transistors;
an input terminal connected to the parallel cell; and
an output terminal connected to the parallel cell,
wherein each gating transistor of the plurality of gating transistors is a ferroelectric FET (FeFET), the FeFET comprising a ferroelectric capacitor (FeCap) and an underlying FET, wherein the FeCap is connected to a gate of the underlying FET, and
wherein the FeCap comprises a pair of titanium nitride (TiN) electrodes and a hafnium zirconium oxide (HfZrO 2 ) ferroelectric layer between the pair of TiN electrodes.
10. The neuromorphic weight cell of claim 9 , wherein the FeCap of each FeFET is at a metal layer in a back-end-of-line of the neuromorphic weight cell.
11. The neuromorphic weight cell of claim 10 , wherein the metal layer is lowermost metal routing layer M 0 .
12. The neuromorphic weight cell of claim 9 , wherein the FeCap of each FeFET is at an insulating layer in a back-end-of-line of the neuromorphic weight cell.
13. The neuromorphic weight cell of claim 12 , wherein the insulating layer is lowermost insulating layer V 0 .
14. The neuromorphic weight cell of claim 9 , further comprising:
a selector line connected to the plurality of programming input lines; and
a plurality of selector transistors at junctions between the selector line and the plurality of programming input lines.