Methods and apparatus to manage workload memory allocation
Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example apparatus includes a workload controller to log instances of access to data records in a log, the workload controller to identify, from the log, a first set of the data records to be migrated to a first memory and a second set of the data records to be migrated to a second memory based on frequencies at which the data records were accessed during a runtime, and a memory manager to migrate the first set of data records to the first memory, and migrate the second set of data records to the second memory.
1. An apparatus to assign memory utilization based on data record demand during a workload execution, the apparatus comprising:
a data element identifier to identify instances of access to the data record during the workload execution;
a data element tracker to:
identify a first portion of the workload execution associated with a first rate of access to the data record; and
identify a second portion of the workload execution associated with a second rate of access to the data record, the second rate of access greater than the first rate of access; and
a memory manager to:
assign the data record to a first memory during the first portion of the workload execution; and
re-assign the data record to a second memory during the second portion of the workload execution.
2. The apparatus as defined in claim 1 , wherein the data element tracker is to identify at least one of a number of processor stall instances associated with the accesses, or a number of processor cycles associated with the accesses.
3. The apparatus as defined in claim 1 , further including a data element performance calculator to generate a heatmap of the workload execution.
4. The apparatus as defined in claim 1 , further including a code modifier to modify source code associated with the data record, the modified code to cause utilization of at least one of the first memory or the second memory.
5. The apparatus as defined in claim 4 , wherein the code modifier is to at least one of modify binary associated with the source code or invoke a dynamic just-in-time (JIT) compiler associated with the source code.
6. The apparatus as defined in claim 1 , wherein the second memory exhibits a latency lower than a latency of the first memory.
7. The apparatus as defined in claim 6 , wherein the memory manager is to reduce a duration of the workload execution in response to assigning the data record to the second memory.
8. A system to assign memory utilization based on data record demand during a workload execution, the system comprising:
means for identifying instances of access to the data record during the workload execution;
means for tracking:
a first portion of the workload execution associated with a first rate of accesses to the data record, and
a second portion of the workload execution associated with a second rate of accesses to the data record, the second rate of accesses greater than the first rate of accesses; and
means for assigning the data record to a first memory during the first portion of the workload execution, the assigning means to re-assign the data record to a second memory during the second portion of the workload execution.
9. The system as defined in claim 8 , wherein the means for tracking is to count at least one of a number of processor stall instances associated with the accesses, or a number of processor cycles associated with the accesses.
10. The system as defined in claim 8 , further including means for generating a heatmap of the workload execution.
11. The system as defined in claim 8 , further including means for modifying source code associated with the data record, the modifying means to cause utilization of at least one of the first memory or the second memory.
12. The system as defined in claim 11 , wherein the modifying means is to at least one of modify binary code associated with the source code, or invoke a dynamic just-in-time (JIT) compiler associated with the source code.
13. The system as defined in claim 8 , wherein the second memory exhibits a latency lower than a latency of the first memory.
14. The system as defined in claim 13 , wherein the assigning means is to reduce a duration of the workload execution in response to re-assigning the data record to the second memory.
15. At least one non-transitory computer readable medium comprising machine-readable instructions that, when executed, cause at least one machine to, at least:
identify instances of access to a data record during a workload execution;
identify a first portion of the workload execution associated with a first rate of accesses to the data record;
identify a second portion of the workload execution associated with a second rate of accesses to the data record, the second rate of access greater than the first rate of access;
assign the data record to a first memory during the first portion of the workload execution; and
re-assign the data record to a second memory during the second portion of the workload execution.
16. The at least one non-transitory computer readable medium as defined in claim 15 , wherein the machine-readable instructions, when executed, cause the at least one machine to characterize the accesses to the data record to identify at least one of a number of processor stall associated with the accesses, or a number of processor cycles associated with the accesses.
17. The at least one non-transitory computer readable medium as defined in claim 15 , wherein the machine-readable instructions, when executed, cause the at least one machine to generate a heatmap of the workload execution.
18. The at least one non-transitory computer readable medium as defined in claim 15 , wherein the machine-readable instructions, when executed, cause the at least one machine to modify source code associated with the data record, the modified source code to cause utilization of at least one of the first memory or the second memory.
19. The at least one non-transitory computer readable medium as defined in claim 18 , wherein the machine-readable instructions, when executed, cause the at least one machine to at least one of modify binary associated with the source code, or invoke a dynamic just-in-time (JIT) compiler associated with the source code.
20. The at least one non-transitory computer readable medium as defined in claim 15 , wherein the machine-readable instructions, when executed, cause the at least one machine to reduce a duration of the workload execution in response to re-assigning the data record to the second memory.