Semiconductor package device and method of manufacturing the same
In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.
1. A semiconductor package device, comprising:
a substrate having a first surface that comprises a filling region;
a trace disposed adjacent to the first surface of the substrate and continuously surrounding the filling region of the first surface of the substrate;
a structure disposed over the filling region and electrically connected to the substrate;
a barrier element disposed on the trace; and
an underfill disposed on the filling region.
2. The semiconductor package device of claim 1 , wherein the trace comprises a first portion and a second portion, and a width of the first portion of the trace is greater than a width of the second portion of the trace.
3. The semiconductor package device of claim 2 , wherein the first portion of the trace is adjacent to a portion of the filling region where the underfill is applied.
4. The semiconductor package device of claim 2 , wherein a height of the barrier element on the first portion of the trace is greater than a height of the barrier element on the second portion of the trace.
5. The semiconductor package device of claim 4 , wherein a height of the underfill adjacent to the first portion of the trace is greater than a height of the underfill adjacent to the second portion of the trace.
6. The semiconductor package device of claim 1 , wherein the trace is ring-shaped.
7. The semiconductor package device of claim 1 , wherein a contact angle of a material of the barrier element relative to a material of the underfill is equal to or greater than about 25 degrees.
8. The semiconductor package device of claim 1 , wherein the structure defines a cavity exposing a portion of the barrier element, a portion of the first surface of the substrate and a portion of the underfill.
9. The semiconductor package device of claim 8 , further comprising an electronic component disposed on a second surface of the substrate opposite to the first surface of the substrate.
10. The semiconductor package device of claim 1 , wherein the structure comprises an interconnection penetrating the structure and electrically connected to the substrate.
11. A semiconductor package device, comprising:
a substrate having a first surface that comprises a filling region and a non-filling region separated from the filling region;
a trace disposed adjacent to the first surface and surrounding the filling region;
a structure disposed over the substrate and electrically connected to the substrate;
a barrier element disposed on the trace; and
an underfill disposed on the filling region, wherein the barrier element protrudes beyond a surface of the structure facing the first surface of the substrate.
12. The semiconductor package device of claim 11 , wherein the trace comprises a first portion exposed from the structure and a second portion covered by the structure, and wherein a width of the first portion is greater than a width of the second portion.
13. The semiconductor package device of claim 12 , wherein a height of the barrier element on the first portion of the trace is greater than a height of the barrier element on the second portion of the trace.
14. The semiconductor package device of claim 13 , wherein a height of the underfill adjacent to the barrier element on the first portion of the trace is greater than a height of the underfill adjacent to the barrier element on the second portion of the trace.
15. The semiconductor package device of claim 11 , wherein the trace is ring-shaped.
16. The semiconductor package device of claim 11 , wherein the structure defines a cavity exposing a portion of the barrier element, a portion of the first surface of the substrate and a portion of the underfill.
17. The semiconductor package device of claim 16 , further comprising an electronic component disposed on a second surface opposite to the first surface of the substrate.
18. The semiconductor package device of claim 11 , wherein the structure includes an interconnection penetrating the structure and electrically connected to the substrate.
19. The semiconductor package device of claim 11 , wherein the trace comprises a plurality of sections, and each section is separated from another section.
20. The semiconductor package device of claim 19 , wherein each section of the trace is separated from each other section of the trace.
21. A semiconductor package device, comprising:
a substrate having a first surface that comprises a filling region;
a trace disposed adjacent to the first surface of the substrate and surrounding the filling region of the first surface of the substrate;
a structure disposed over the filling region and electrically connected to the substrate;
a barrier element disposed on the trace; and
an underfill disposed on the filling region;
wherein the trace includes multiple sections, and each section is separated from at least one other section; and
wherein the multiple sections together form a pattern surrounding the filling region of the first surface of the substrate.
22. The semiconductor package device of claim 21 , wherein each of the multiple sections comprises a first portion and a second portion, and a width of the first portion is greater than a width of the second portion.
23. The semiconductor package device of claim 22 , wherein the barrier element is disposed on the first portion and the second portion, and a height of the barrier element on the first portion is greater than a height of the barrier element on the second portion.