IP Library Granted Patent US 10,128,353
Granted Patent B2
US 10,128,353 · App. 15/809,863 · Granted Nov 13, 2018

Trench transistors and methods with low-voltage-drop shunt to body diode

Inventors: Mohamed N. Darwish (Campbell, CA); Jun Zeng (Torrance, CA); Richard A. Blanchard (Los Altos, CA)
Assignee: MaxPower Semiconductor Inc.
H01L29/66734H01L21/26506H01L21/823412H01L21/823437H01L21/823475H01L21/823487H01L27/088H01L29/0878H01L29/1033H01L29/1095H01L29/16H01L29/36H01L29/407H01L29/41741H01L29/41766H01L29/4236H01L29/66727H01L29/7395H01L29/7803H01L29/7813H01L29/7827H01L29/7831H01L29/7835H01L29/0623H01L29/0634H01L29/0847H01L29/42368H01L29/66666
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,128,353
App. No.
15/809,863
Granted
Nov 13, 2018
Kind
B2
Abstract

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Claims (19)

1. A power semiconductor device, comprising:

a first-conductivity-type source region;

a first trench containing a gate electrode which is capacitively coupled to a body region to selectably form a channel region therein;

at least one second trench containing a recessed field plate electrode;

a body contact region which is more heavily doped than said body region;

a plurality of shield regions; wherein one said shield region is present beneath at least each said second trench;

a source metallization layer which is in ohmic contact with said source region and said body contact region, and which is electrically connected to said gate electrode; and

a backside metallization layer.

2. The device of claim 1 , wherein one said shield region is present beneath said first trench.

3. The device of claim 1 , wherein said body contact region extends to one said shield region.

4. The device of claim 1 , wherein said gate electrode is a split gate electrode.

5. The device of claim 1 , wherein said shield regions are second-conductivity-type regions.

6. The device of claim 1 , wherein said first trench has a thick bottom oxide.

7. The device of claim 1 , wherein said first conductivity type is N type.

8. The device of claim 1 , further comprising first and second wherein each said first trench-gated transistors, and wherein each said first trench-gated transistor has a lower threshold voltage than each said second trench-gated transistor.

9. The device of claim 8 , further comprising at least one field plate electrode separating said trench-gated transistors.

10. The device of claim 1 , further comprising a second-conductivity-type shield region beneath at least one said gate electrode.

11. The device of claim 1 , wherein at least one said gate electrode is a split gate electrode.

12. The device of claim 1 , constructed in a semiconductor die which is made of silicon.

Assignments (1)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →
Continuity (4)
Continuation 14677511 · Apr 2, 2015
Continuation 13758689 · Feb 4, 2013
Provisional Application 61597979 · Feb 13, 2012
Related Publication 20180138293A1 · May 17, 2018